x86 task switching with invalid TR descriptor cache?

Emulation of old PCs, PC hardware, or PC peripherals.

x86 task switching with invalid TR descriptor cache?

Postby superfury » 2019-6-17 @ 19:57

What happens when a hardware task switch is done(using interrupt gate, task gate, TSS or IRET in any way) without LTR having executed at first? The docs only talk about the loaded(destination) task descriptor etc., but what about an not-present(thus uninitialized, in it's RESET state) TR descriptor(a non-present data descriptor set during RESET) during a triggered task switch? I notice some Linux distribution doing this somehow? Linux seems to dot this with an IRET in UniPCemu's case? I believe it was either the Pragma Linux or OpenBSD version floppy disk from Bochs' disk image page.

Edit: Nope. It's Basic Linux 3.50(the latest(final) 1.44MB floppy version). From https://distro.ibiblio.org/baslinux/ . Although the BIOS settings (Compaq Deskpro 386) are configured as 720K instead of 1.44MB due to lack of BIOS support for 1.44MB drives(and '720K' CMOS 10h settings(value 53 decimal) fixes the track seeks required for 1.44MB disks).
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Re: x86 task switching with invalid TR descriptor cache?

Postby superfury » 2019-6-18 @ 12:46

Perhaps an undocumented #TS(TR) occurs(I've just modified UniPCemu to act in this way, as a TSS being incorrect is actually used)? Anyone can check said behaviour using a normal task switch and using an IRET on an actual CPU? What happens in that case?
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