First post, by superfury
What happens when a TLB miss is detected, a new PDE(with PTE for 4KB page size) is fetched from memory and to be stored into the TLB, but the TLB already contains an entry for said address of the opposite page size? So when a 4KB page is found in memory(PDE+PTE) and the PDE that's fetched is a 4MB PDE? And the reverse (A 4MB is in the TLB, but a 4KB TLB is fetched)?
Is the opposite TLB invalidated(4MB in the case of a 4KB PTE and 4KB in the case of a 4MB PDE)? Are both the 4KB PTE and 4MB PDE cached(which has some priority applied to it, on which one is to be used for a linear address e.g. 4MB over 4KB or 4KB over 4MB)?
Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io