So, what Dosbox (and UniPCemu now too) does is:
- Take the don't care planes from the latch(where don't care is set). This leaves the latches' planes set for the don't care bits.
- Take the color compare planes to compare(where don't care is set). This generates the color compare planes' comparison bits for the don't care of a plane when set, Clearing color_dont_care will cause the result to always be 0 for said plane, causing the resulting bit to be set to 1. Setting it, on the other hand, makes it compare the latch against the color compare. When it isn't equal, the result will (because of the final bit flip) become cleared. Otherwise, the result will become 1 for said bit.
Then, it's when any of the four planes don't match or the color compare for such a plane is cleared, but otherwise it's set?
So that would make both our implementations correct now?
And indeed, the only remaining thing is to know how the non-planar modes handle it.
I suspect that UniPCemu's ways of doing it is the correct one now. Since the read and write modes seem unaffected by the access method(odd/even vs chain-4 vs planar), said plane/offset generation must be in a seperated part of logic from the read/write modes themselves.
I can also in not a single documentation see that the two are having any effect on each other. The plane/offset generation is documented. The plane/offset using read/write modes are documented. So it only makes sense that the two are fully seperated parts on the (S)VGA chip, their modes having no direct effect on the other(e.g. 256 color shift(as Dosbox implements it) having not a single direct effect on the read/write mode transformation).
The whole process is likely about the same way UniPCemu implements it. The MA is converted to a plane and a memory address, according to the offset transformation setting(odd/even, planar or chain-4). The next step is taking the generated planes and offset and transforms it onto/from VRAM using the selected read/write mode.
So, what Dosbox does(handling read modes/write modes different in Chain 4 vs odd/even vs planar modes) is incorrect. The two-step translation(1. MA -> plane&offset, 2. plane&offset=>VRAM/latch) is very likely the way a VGA card also handles it. Although maybe intergrated on a single chip nowadays, and perhaps seperated on die on the VGA chips itself.