Thank you very much! The ESS one is especially useful, as for one, it clearly calls the MPU-401 queue a FIFO, and also talks about a transmit FIFO as well. Now I need to read the NS16550 UART datasheet to see how FIFO IRQ's behave there (maybe I'm misrememebring something), becaue while this is not a NS16550, it should be behaving pretty similarly regarding IRQ's.
Edit: The NS16550 datasheet says this:
In non-FIFO mode, there is received data available in the RHR register.
In FIFO-mode, the number of characters in the reception FIFO is equal or greater than the trigger level programmed in FCR.
Note that this is not directly related to LSR bit 0, which always indicates that there is at least one word ready.
I know that the MPU-401 receive status bit corresponds to the 16550's LSR bit 0, so what remains is how the IRQ works. I remember a "Programming the MPU-401" PDF saying that on receiving the interrupt, you should read until the status bit indicates there's no more data available, which means that the interrupt should occur on FIFO full, ie. on the last byte. However, the DOSBox MPU-401 code raises an IRQ on the first byte. I need to read up more on this.
Edit #2: The whole statement from the ESS datasheet:
The MPU-401 interrupt occurs when a MIDI byte is received. It goes low when a byte is read from the MIDI
FIFO and goes high again quickly if there are additional bytes in the FIFO.
I suppose that it keeps receiving bytes after one is read, and if after reading and lowering the IRQ, additional bytes are available, it immediately raises an IRQ again.