When is the bus released for a DMA transfer to be able to start on the T1 cycle? Is after every T4-T1 cycle? Or do things like word transfers make the DMA controller wait for the next T1 cycle when the latter half of the word is still to be transferred(it's only acnowledged by the CPU when no byte/word transfer is started yet)?

So when exactly does the CPU raise HLDA? Is it after every byte transfer on the 8088? Or after any byte/word transfer in total(so a HLDA will only be raised after the full word is transferred)?