I know that the CPU reset pin is connected to the i440fx.

What I'm wondering about right now is this: is the IO APIC reset line also connected to said CPU reset pin? Or is the IO APIC reset pin only triggered when performing a hard reset from software(actual reset of the emulated machine(from the user interface) or through the port CF9 register's hard reset functionality, by setting bit 1 and 2 together(triggering a hard reset instead of a soft reset))?

It used to be on all CPU resets, but I've just changed it to trigger by port CF9 bit 2 being set for that kind of reset only(as well as the emulator being initialized)? Would that be correct behaviour?
Bochs seems to imply this is the case(seeing as the reset type only in that case is the HARD type of reset(instead of SOFT))?