Real mode(MS-DOS 6.22) polldac still reports o2h.
WhatVGA 2.00 says Sierra SC11487.
UniVBE says "HiColor 15 bit DAC" (w/o quotes).
There's still the weird case of bits 1-4 in the RAMDAC CMD register.
WhatVGA says that bit 3-4 are the PEL mask bits. But clearing those in the PEL register and then setting it in the CMD register with the CMD register, finally reading it back set(bit 4) causes WhatVGA to detect a "'Trident TKD8001" instead.
WhatVGA says this:
bit 0 (SC11487) (R) Set if bits 5-7 is 1 or 3, clear otherwise
3-4 (SC11487) Accesses bits 3-4 of the PEL Mask registers (REG02)
But it's source code disapproves about bit 4?
WhatVGA's code at https://www-user.tu-chemnitz.de/~kzs/tools/whatvga/idvga.pas at least approves of the bit 0 behaviour.
But, for the SC11487, bits 1-4 could all simply be a r/o passthrough to the DAC mask register. Bit 4 at least has to be(for that detection to work). But bits 1-3 are either always set, probably fully settable(documentation says nothing on it) or more simply all passed through to the PEL mask register?
Edit: It also looks like bit 0 on the SC11487 is only set when trying to use two clocks per pixel without 16-bit color mode active(latching 2x8 bit for an 8-bit PEL mode). And of course that's invalid to do. So it sets bit 0 in that case. So it's kind of an error flag.
Edit: Hmmm... Case 01h is invalid in this case and 02h is correct: 01h is a SC1146[1/6/8], which this isn't(SC11487).
Edit: Just have been searching some more. Eventually found the dr Dobbs journal entry on it's detection:
https://www.drdobbs.com/database/sourcecode/g … amming/30401306
It does this:
It switches to DAC mode, sets the command register to 0x00 and DAC mask to 0xFF, switches to command register and expects it to not be 0xFF(the mask). It also notes that the 0 in the command register should be read back.
So when both that and WhatVGA is supposed to work, since the DAC mask is fully set and clearing it should clear bit 4 according to WhatVGA, while setting the mask register but clearing the command register should read back 0x00, that would mean that the command register bits are mostly running normally(returned as-is). The only exception being bit 0(the error bit) and bit 4(which needs to clear in the read result if the mask bit is also cleared). So the bits in the command register is to be written normally, but the reading of bit 4 would have to be masked by the clearing of the mask register. That way, both cases would work as documented?