Just read the SC15025 datasheet...
Holy ....! Those lower bits pack a lot of functionality! Although it would be interesting to emulate for it's 4-byte RGB(not RGBA) modes(UniPCemu only implements 3-byte RGB modes and RGBA using 4-bytes(although never set by the DAC emulation)). So that would make the 4-byte aligned RGB 320x200 a possibility if emulated(640x400 at the most), with the plain ET4000AX.
So, in other words, bit 4 enables extended registers at the color registers space, bit 3 enables LUT(the DAC palette registers) translation for the R/G/B inputs in 15/16/24-bit color modes, bit 0 enables extended 15-bit(in 15-bit mode) or BGR(in 24-bit mode) modes when using 24-bit pixels. 24-bit mode is set by bit 6 without bit 7(in addition to the modes WhatVGA documents for the SC11487). Bits 7&5 act as documented by WhatVGA(16/15-bit enable and 2 clocks latching for 16-bits instead of during 1 clock for 16-bits). Bit 6 enables 16-bit mode instead of 15-bit mode when bit 7 is set. Otherwise, it enables the RGB/BGR modes.
When the LUT translation in the 15/16-bit modes is enabled, bits 1&2 are shifted right(essentially) into the R/G/B inputs for 15/16-bit modes. Extended 15-bit mode just then sets bit 0 to bit 15.
The final step it seems to perform in LUT translation is putting each of the R, G and B as an index into the DAC LUT itself(accessed from ports 3c7/3c8/3c9 in VGA-compatible mode) to obtain their DAC values for the R(taking the red channel), G(taking the green channel) and B(taking the blue channel) for the actual RGB value.
And before performing any and all of the translation(for LUT mode), the entire input is masked with the 24-bit mask in the extended registers(0F0E0Dh (the numbers in xxyyzzh are the extended register numbers which fill these bits)'s value in little endian), which by default has all bits set(poweron/reset). When LUT mode isn't set(clearing command register bit 3), the mask is applied to the 15/16/24-bit input value instead.
Extended register 08h bit 0 enables 8-bit DAC when set. Registers 09-0C are ROM containing 0x53, 0x3A, 0xB1, 0x41 for identification And register 10h bit 0 adds a 4th discarded byte input in RGB/BGR modes that is discarded for a 0RGB or 0BGR mode to be createn(32BPP).
That about seems to sum it up?
Edit: Also (when the bit 4 is set at the command register):
Palette RAM write address register = Extended data registers(r/w)
Palette RAM read address register = Extended index register (write only)
Palette RAM data = Extended index register (read only)
So that's about a complete documentation in readable format on the chip specs of the SC15025's registers and it's rendering. If combined with the information about the SC11487 in the WhatVGA documents(RAMDAC.TXT), it'll be an easily parsable documentation on the SC15025 chip and how it's programmed.