Reduced the port 217B back to being a 8-bit I/O port only responding to said port for reads and writes.
Also implemented the image port to map to the selected VRAM addresses (row widths of 0 keep it stuck to the first scanline for any scanline following it). This is done by a simple divide and modulo operation to determine the VRAM address added to the start address in the IMA registers.
So all that's currently left is the actual implementation of the raster operations, which is currently unknown? The W32i documentation gives a ROP list, but I don't know anything about how it works?
Edit: Appearently it's just a mask determining if a bit is to be masked? So the destination masks it's odd bits, source it's odd/higher half nibbles and pattern it's odd nibbles. Anding all those masks together with the Raster Operation(like ROP&destmask&srcmask&patmask), when any bits are left set(the even/odd bits/half nibble/nibble selected by the destination bit, source bit and pattern bit respectively) the resulting bit in the result is set.
UniPCemu now retrieves the bit(using simple preshifted mask) from all three, inputs them to the three mask inputs(to get 55/aa(destination); 33/cc(source) and 0f/f0(pattern), anding them with each other and the ROP used. Then, if it has a set bit(thus non-zero), it will set the respective bit that was an input to the odd/even checks in the result. The inputs to the odd/even checks is simply a left-shifting value from 0x01 to 0x80(reaching 0x100 stops processing). Although it can maybe be optimized from ((x!=0)&1) to (x>>i) when adding a second counter to the loop.
Since, according to the ET4000/W32i documentation, the LineDraw doesn't exist on the ET4000/W32(i), it means it's (together with all other ET4000/W32 functionality) now fully implemented the algorithm (although no wrapping is supported yet so far).
One thing I did implement is that while the terminating operation is like documented, the suspend operation still requires sending leftover data before it's suspended(remainder of pixels for a running transfer) and will suspend on completion of said part of the operation (maybe requiring inputting CPU data).