It's indeed Tseng-specific behaviour. All other graphic card(including IBM VGA) just use the Sequencer Mode Control register bit. Tseng also doesn't call the GDC bit by it's normal name(256-color shift mode (loading for the latches when rendering)), but calls it linear graphics(LG) mode because it also enforces CPU addressing using byte addressing mode for loading during rendering, breaking VGA compatibility with demos as is well known (which is less documented).
"6 Enable 256 color mode"
"Bit 6 When set to 0, permits the loading of the ATC's shift registers to be controlled by bit 5.
When set to 1, the registers are loaded to support the 256-color mode."
Note that it doesn't say shift registers the second time, probably because it does a lot more than that(chain 4 and byte addressing mode being included/enforced to be exact).
Then there's the many times it lightly documents the LG/Linear Graphics mode throughout the document in many 8-bit scenarios, which is quite confusing and only adds to the ambiguity.
TS index 4 adds to that:
"Bit 3 When set to 1, will enable Chain 4 (linear graphics) mode"
So it implies (and register dumps in the document for the various modes confirm) that the two bits are OR'ed together for Chain 4 mode to become active.
Edit: GDC and TS registers are loaded as in VGA on W32 chips. ET4000AX loads GDC and TS as VGA as well?
But, the 8-bit mode of the attribute controller mode control register is only set during mode 13h, but not all other 8-bit modes.
So according to the documentation, only the attribute mode control is different from specs, with it being setup differently by the BIOS and drivers(they also use the linear mode bit in the extended ET4000 registers instead?). It's also differing with the 8-bit and linear modes(1 clock/byte instead of 2(VGA/mode 13h) during LG mode) from VGA.
For a more simple explanation on how I implemented the various Tseng addressing modes, look at UniPCemu's tseng.c and search for the locations using the linearmode precalc.
There's a lot that's combining together to form the actual mode it seems (both for rendering and CPU):
- ET3000 1M linear memory mode(segment select register high 2 bits=2 or 3).
- ET4000 linear system configuration bit (bit 4 of system configuration 1).
- ET4000 bit 5 of system configuration 1(contiguous mode).
- Sequencer memory mode register bit 3.
- Graphics mode register bit 6.
- Attribute mode control register bit 6(having only effect on rendering).
- Sequencer clocking mode register bit 3 (and bit 1 is wrongly set instead in some modes on ET3000) for Dot Clock Rate division.
Those are all factoring in together in determining the memory map the CPU sees and how the Tseng chip addresses VRAM for rendering.
It's kind of complicated how UniPCemu combines all those, so look at tseng.c for the actual way they seem to combine (verified using the actual ET4000AX and ET3000AX BIOSes).