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UniPCemu 8088 cycle accuracy

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Reply 40 of 122, by GloriousCow

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superfury wrote on 2023-07-16, 21:31:

Is the immediate being fetched in the instruction itself a common behaviour? Or more of an exception? It complicates disassembly though.

It's the behavior of any instruction with a 'rm, imm' form. The decode in general doesn't know about ANY operands that aren't a modrm; it just decodes prefixes, opcodes, and modrm bytes, and then runs the appropriate microcode, blissfully unaware of whether the resulting instruction is going to fetch an immediate or a far pointer or a three headed monkey.

You're right it makes disassembly harder; i posted about how I handle that above.

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 41 of 122, by superfury

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GloriousCow wrote on 2023-07-16, 22:37:
superfury wrote on 2023-07-16, 21:31:

Is the immediate being fetched in the instruction itself a common behaviour? Or more of an exception? It complicates disassembly though.

It's the behavior of any instruction with a 'rm, imm' form. The decode in general doesn't know about ANY operands that aren't a modrm; it just decodes prefixes, opcodes, and modrm bytes, and then runs the appropriate microcode, blissfully unaware of whether the resulting instruction is going to fetch an immediate or a far pointer or a three headed monkey.

You're right it makes disassembly harder; i posted about how I handle that above.

OK. So I'll just need to remove the immediate operands from the generic fetching/decoding handlers and move them to be called at the EU instruction handler level instead. And ofc disassembly performing only after fetching those. That'll require basically all immediate-using instructions to be adjusted though.

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Reply 42 of 122, by GloriousCow

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Also it goes without saying perhaps, this behavior may be specific to the 8088/8086. I can't speak for how the 286+ decodes things.

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Reply 43 of 122, by superfury

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GloriousCow wrote on 2023-07-17, 12:54:

Also it goes without saying perhaps, this behavior may be specific to the 8088/8086. I can't speak for how the 286+ decodes things.

Well, luckily it's relatively easy to implement. Although it's a lot of search and insert work to call a new function I've made at all imm-using functions.
Then after that it's just a matter of disabling the imm handler call on the 8086 that's called after the modr/m and displacement to enable that behaviour on the 808x CPUs.

It´s about 180 new lines that need to be inserted into all functions using the immediate atm. I´ve already implemented the function to be called in the CPU general handling. It´s just a matter of adding the call to read the immediate at those 180 locations throughout all EU code and then disabling the main call that´s still done at the fetching stage.
Luckily the fetching stage works in roughly the same way as the EU handler, just being hardcoded to run before the instruction-specific parts, so it can be easily ported to said locations.

Edit: Added the function call before all instructions.
I've noticed a slight issue now: when an modr/m is used, usually the relevant function is done as a subfunction, where the immediate is passed to the generic function handler BEFORE the function call, which fetches said modr/m itself.
So now i'll need to add special functionality to all those functions that handle the modr/m to instead fetch their actual parameters and actually sign extend etc if needed.
Since it's so common, it would probably simply need a variable to store that says if to sign extend or take a smaller version (8-bit to 16-bit/32-bit special extensions).
That'll be a bit more time to implement.
Edit: It's implemented, but still a broken implementation (it won't POST anymore atm).
Edit: Hmmm... It's gettting to execute at CS=0 almost right away. That shouldn't happen....
Also, this issue doesn't affect the 286+ CPUs, as they handle the immediate during the modr/m fetching phase instead (the old behaviour), so they POST just fine.
Edit: OK. It seems to be crashing on an interrupt 1Ch jumping to segment 0?
Said interrupt is jumping to 0000:FF53, which shouldn't happen.
Edit: I see it entering an #UD instruction (undefined) of C7 0B, which is C7 /1, which doesn't exist?
Perhaps it's RETing to the wrong byte in memory? So that would make one of the CALL instructions the cause?
Edit: It actually was the issue: the CALL would first PUSH the IP (before the reading of the immediate), then read the immediate and jump to it based on the new IP. But since the push didn't take the immediate into account (it wasn't read yet), it would RET into the immediate instead of after the immediate at a later point in execution of the BIOS ROM!

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Reply 44 of 122, by superfury

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The EA timings are now also done directly after the modr/m byte and displacement, instead of after the immediate (still in the same place in the EU code, just because the immediate is moved to the EU instruction handler it's moved in between the two). It's still after the immediate on 286+ CPUs.

Edit: Just checked you EA timings table. It matches what UniPCemu now inserts between the modr/m byte+displacement and the EU handler (when the instruction is usually logged, unless it's delayed by immediate fetching at a later point in time (essentially when it starts using it)).

Edit: Latest 8088tst3 results:

disk:	real:	comp-d:	disp1:	comp1:	disp2:	comp2:	disp3:	comp3:	disp4:	comp4:	disp5:	comp5:
FF36 FF43 <(-13) FF36 <(-13) FF36 <(-13) FF46 >(+3) FF48 >(+5) FF47 >(+4)
FE3C FE59 <(-29) FE3D <(-28) FE3D <(-28) FE61 >(+8) FE65 >(+12) FE66 >(+13)
FDA0 FDC5 <(-37) FDA1 <(-36) FDA3 <(-34) FDD3 >(+14) FDD7 >(+18) FDD7 >(+18)
FD26 FD58 <(-50) FD27 <(-49) FD28 <(-48) FD63 >(+11) FD67 >(+15) FD67 >(+15)
FCF7 FD2A <(-51) FCF8 <(-50) FCF8 <(-50) FD37 >(+13) FD3C >(+18) FD3D >(+19)
FC31 FC6B <(-58) FC31 <(-58) FC31 <(-58) FC81 >(+22) FC87 >(+28) FC88 >(+29)
FB6D FBB7 <(-74) FB6E <(-73) FB6D <(-74) FBCD >(+22) FBD2 >(+27) FBD4 >(+29)
F93C F9A9 <(-109) F93D <(-108) F93D <(-108) F9C9(+32) F93E >(+32) F9DE >(+53)
CPU test complete. Elapsed timer ticks:
07F1 07CA <(+27) 07F2 <(+28) 07F1 <(+27) 074D <(-125) 0735 <(-149) 0733 <(-151)

Edit: 8088 MPH credits once again crash (if run standalone at least).

Edit: Just fixed the final prefetch cycle of instruction or modr/m (whichever is the last of the EU default instruction fetching process) to properly take 1 cycle instead of being ignored in timing. So that would add 1 cycle to each intruction properly (for the final byte/word/dword fetched from the PIQ).
Previously (above table) that would be taking 0 cycles effectively (untimed clock tick).
Edit: OK. Implementing that final clock tick made it hang once again 😖 Although not instruction-wise but data-wise it seems? It keeps executing INT 16h calls with function call (AH) being 01h in an infinite loop?

Edit: OK. There was an issue with hardware interrupts (INTA cycles to be exact). It was triggering the CPU to fetch a new instruction after the (second on 808x, first on 286+) INTA got the interrupt vector through the BIU because it wasn't clearing the new instruction flag that triggers the PIQ to be used for an new instruction.

With that fixed, it POSTs again! 😁

Edit: Latest 8088tst3 results:

disk:	real:	comp-d:	disp1:	comp1:	disp2:	comp2:	disp3:	comp3:	disp4:	comp4:	disp5:	comp5:	disp6:	comp6:
FF36 FF43 <(-13) FF36 <(-13) FF36 <(-13) FF46 >(+3) FF48 >(+5) FF47 >(+4) FF44 >(+1)
FE3C FE59 <(-29) FE3D <(-28) FE3D <(-28) FE61 >(+8) FE65 >(+12) FE66 >(+13) FE60 >(+7)
FDA0 FDC5 <(-37) FDA1 <(-36) FDA3 <(-34) FDD3 >(+14) FDD7 >(+18) FDD7 >(+18) FDD1 >(+12)
FD26 FD58 <(-50) FD27 <(-49) FD28 <(-48) FD63 >(+11) FD67 >(+15) FD67 >(+15) FD5F >(+7)
FCF7 FD2A <(-51) FCF8 <(-50) FCF8 <(-50) FD37 >(+13) FD3C >(+18) FD3D >(+19) FD33 >(+9)
FC31 FC6B <(-58) FC31 <(-58) FC31 <(-58) FC81 >(+22) FC87 >(+28) FC88 >(+29) FC7D >(+18)
FB6D FBB7 <(-74) FB6E <(-73) FB6D <(-74) FBCD >(+22) FBD2 >(+27) FBD4 >(+29) FBCB >(+20)
F93C F9A9 <(-109) F93D <(-108) F93D <(-108) F9C9 (+32) F93E >(+32) F9DE >(+53) F9D2 >(+41)
CPU test complete. Elapsed timer ticks:
07F1 07CA <(+27) 07F2 <(+28) 07F1 <(+27) 074D <(-125) 0735 <(-149) 0733 <(-151) 0745 <(-133)

Edit: 8088 MPH reports 1606 cycles now! Getting closer!
Edit: 8088 MPH credits run again (just a simple standalone executable check though, by renaming 8088MPH.D to 8088CRE.EXE)!
After running 8088MPH, FD33 becomes FD34 sometimes? And elapsed timer ticks becomes 0744 with FD34 being there?

Last edited by superfury on 2023-07-18, 19:48. Edited 1 time in total.

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Reply 45 of 122, by superfury

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Interestingly now the noise on the 16/256 colors of 8088 MPH seems to have moved to the 3rd character clock?
Proven by moving the CGA to RGB mode. It's indeed the 3rd character clock that has noise now.

Edit: It looks like 8088 MPH's racing the beam just has those fixed intervals left now:

26-UniPCemu_20230718_KefrensFixedIntervals.png
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Kefrens showing displacements on fixed intervals.
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If you look at the gaps (Either black or some of the other colors), you'll see that they seem to be at fixed lengths (or sometimes exactly twice that)?

Looking closely, it also looks like the bottom scanline is slowly moving from being black into more of a coloured scanline (it creeping a bit more to the right side of the window every frame or so, like a percentage of a file copying process that's slowly filling the bar (about 1 percent every 1 or 2 seconds...

Edit: It might also be the kefrens effect overshooting?

Edit: A short capture of the Kefrens effect running inside UniPCemu's latest commit:
https://www.dropbox.com/s/stkpm99tz2mwi05/Uni … 1-24-44.7z?dl=0

Edit: And the credits also run within the demo itself without any visible problems.

The credits audio is also a lot cleaner than it was on the last Youtube recording of it running I made (https://www.youtube.com/watch?v=8aOhDyys2NY&t=538s). Most of the noise signal that's in the front there is now just a slight hiss in the background.

Edit: Interestingly I count 80 (right hand side) and 72 (left hand side) pixels of overscan during the 3D glass ball effect of Area 5150? That probably shouldn't be the case? So the right hand side is 9 character clocks wide, while the left hand side is 10 character clocks wide?

The same with the elephant dancing part?

Edit: What is the value of the sync width register? Is it ending sync the specified amount of character clocks after the horizontal retrace start? What if it's set to 0?

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Reply 46 of 122, by superfury

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About the sync width register, does anyone know how it operates exactly on the CGA?

Also, does the horizontal total register on CGA specify the column at which the counters are reset? So if specifying 80h, on the 128th character clock's first pixel clock the counter will reset and instead perform the 0th character clock?
Is that correct behaviour?

As a little side-note, I've made a little program (in NASM assembly) that simply increases the overscan color register's value.
It should properly detect a CGA or VGA (VGA being detected using the MC6845's CRTC index register undefined bits being zeroed or 0xFF being returned for selecting the VGA's 24h register (which contains the attribute controller index register together with the flipflop, which is used to cleanup to the flipflop state after writing the overscan color)).
Said program simply reads the current color from the CGA/VGA (attribute) color register, increases it (modulo 16 on CGA/MDA, modulo 64 on EGA/VGA) and writes it back to the register, then reverting the CRTC registers and (on EGA/VGA only) the attribute index register (together with the flipflop, unless on EGA, where the previous state is undetectable (always flipflop left as set)).

So each execution of said program will increase the border color's register value (and using a specific modulo when writing it back, leaving other bits unmodified).
You can use it to test the overscan color in emulators or real graphics cards (in theory at least, unless it misdetects the hardware). I've only tested it on an emulated (like a real) CGA and VGA though inside UniPCemu.

The main nice thing I'm using it for right now is to check where overscan starts and stops, as the overscan is usually 0, thus invisible against a black MS-DOS window (except if there's text on the first character of the scanline, where the left hand overscan is visible).

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Reply 47 of 122, by superfury

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With 80 column (at bootup, after MS-DOS displays itself) text mode, I see it's executing 640 pixel clocks of active display, 10 clocks of overscan, 10 clocks of horizontal retrace, then 14 clocks of overscan until horizontal total at clock #114 (which is then the next clock #0 of the next scanline.

Can anyone tell me if that's correct?
The CGA CRT registers are as follows:
00=71h
01=50h
02=5Ah
03=0Ah
04=1Fh
05=06h
06=19h
07=1Ch
08=02h
09=07h
0A=06h
0B=07h
0C=00h
0D=00h
0E=05h
0F=F4h
10=00h
11=00h

Looking at an earlier post:
Re: CGA Timings

I see that horizontal timings should be correct, at least in 40 column text mode.
Vertical is odd though?

Register values after MS-DOS running mode co40 with C:\> displaying at character location 0,4:
00=38h
01=28h
02=2Dh
03=0Ah
04=1Fh
05=06h
06=19h
07=1Ch
08=02h
09=07h
0A=06h
0B=07h
0C=00h
0D=00h
0E=00h
0F=2ch
10=00h
11=00h

CGA mode control being 28h.

Edit: Even looking at those register values seems weird? 38-(2D+A)=1(front porch), 2D-28=5(back porch)? That seems weirdly uncentered?`

8088 MPH reports 1607 cycles (4%) atm btw.
Active display is 640 pixel clocks in both 40 column and 80 column mode, which should be correct? HRetraceStart is at 720 pixel clocks in both cases, which is probably correct? Although 40 column text mode retrace ends at clock #880(clock #110), while 80 column mode it ends at #800(character clock #100)? That difference of 10 character clocks exactly probably isn't a coincidence?
Both end at clock #912 (horizontal total).
Edit: Nope. It doesn't seem to be a coincidence after all:
- Register 02,03 in 80 column mode: 5A, 0A.
- Register 02,03 in 40 column mode: 2D(halved), 0A(the same as 80 column mode)!
So horizontal timing for retrace start applies, but retrace end needs to be halved to work properly on low-res text mode?

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Reply 48 of 122, by superfury

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I notice one thing on 8088 MPH as well though:
When the first screen (which visibly shows the old vs new CGA difference (old vs new CGA) shows, it's displaying incorrectly now?

I think that the issue with the odd/even scanlines on the Kefrens effect might either be an issue with the overscan displaying when it shouldn't on odd scanlines instead of active display, or perhaps the overscan color being set with all pixels being zeroed on those scanlines (which would have the same effect)?

Double checking with the other app that uses (cga compatibility tester)...

Edit: Although the timings themselves look fine, perhaps there's another issue?

Horizontal and vertical clocks used by UniPCemu during the intro screen
00:18:22:44.08000: Row #0=+VRETRACEEND+VBLANKEND+VACTIVEDISPLAY
00:18:22:44.09024: Row #1=+VTOTAL+VACTIVEDISPLAY+VSYNCRESET
00:18:22:44.09152: Col #0=+HRETRACEEND+HACTIVEDISPLAY+WRITEBACK
00:18:22:44.09280: Col #1=+HRETRACEEND+HACTIVEDISPLAY
00:18:22:44.09408: Col #2=+HACTIVEDISPLAY+WRITEBACK
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00:18:22:45.09776: Col #116=+HACTIVEDISPLAY+WRITEBACK
00:18:22:45.09904: Col #117=+HACTIVEDISPLAY
00:18:22:45.09904: Col #118=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.00032: Col #119=+HACTIVEDISPLAY
00:18:22:46.00160: Col #120=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.00288: Col #121=+HACTIVEDISPLAY
00:18:22:46.00288: Col #122=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.00416: Col #123=+HACTIVEDISPLAY
00:18:22:46.00416: Col #124=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.00544: Col #125=+HACTIVEDISPLAY
00:18:22:46.00672: Col #126=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.00800: Col #127=+HACTIVEDISPLAY
00:18:22:46.00800: Col #128=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.00800: Col #129=+HACTIVEDISPLAY
00:18:22:46.00928: Col #130=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.01056: Col #131=+HACTIVEDISPLAY
00:18:22:46.01184: Col #132=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.01312: Col #133=+HACTIVEDISPLAY
00:18:22:46.01312: Col #134=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.01312: Col #135=+HACTIVEDISPLAY
00:18:22:46.01440: Col #136=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.01568: Col #137=+HACTIVEDISPLAY
00:18:22:46.01696: Col #138=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.01824: Col #139=+HACTIVEDISPLAY
00:18:22:46.01824: Col #140=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.01824: Col #141=+HACTIVEDISPLAY
00:18:22:46.01952: Col #142=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.02080: Col #143=+HACTIVEDISPLAY
00:18:22:46.02336: Col #144=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.02336: Col #145=+HACTIVEDISPLAY
00:18:22:46.02592: Col #146=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.02720: Col #147=+HACTIVEDISPLAY
00:18:22:46.02848: Col #148=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.02848: Col #149=+HACTIVEDISPLAY
00:18:22:46.03104: Col #150=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.03360: Col #151=+HACTIVEDISPLAY
00:18:22:46.03360: Col #152=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.03488: Col #153=+HACTIVEDISPLAY
00:18:22:46.03616: Col #154=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.03744: Col #155=+HACTIVEDISPLAY
00:18:22:46.03872: Col #156=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.03872: Col #157=+HACTIVEDISPLAY
00:18:22:46.04000: Col #158=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.04128: Col #159=+HACTIVEDISPLAY
00:18:22:46.04256: Col #160=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.04384: Col #161=+HACTIVEDISPLAY
00:18:22:46.04384: Col #162=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.04512: Col #163=+HACTIVEDISPLAY
00:18:22:46.04640: Col #164=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.04768: Col #165=+HACTIVEDISPLAY
00:18:22:46.04768: Col #166=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.04896: Col #167=+HACTIVEDISPLAY
00:18:22:46.04896: Col #168=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.05024: Col #169=+HACTIVEDISPLAY
00:18:22:46.05152: Col #170=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.05280: Col #171=+HACTIVEDISPLAY
00:18:22:46.05408: Col #172=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.05536: Col #173=+HACTIVEDISPLAY
00:18:22:46.05664: Col #174=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.05792: Col #175=+HACTIVEDISPLAY
00:18:22:46.05792: Col #176=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.05920: Col #177=+HACTIVEDISPLAY
00:18:22:46.05920: Col #178=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.06048: Col #179=+HACTIVEDISPLAY
00:18:22:46.06176: Col #180=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.06304: Col #181=+HACTIVEDISPLAY
00:18:22:46.06304: Col #182=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.06432: Col #183=+HACTIVEDISPLAY
00:18:22:46.06432: Col #184=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.06560: Col #185=+HACTIVEDISPLAY
00:18:22:46.06688: Col #186=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.06688: Col #187=+HACTIVEDISPLAY
00:18:22:46.06816: Col #188=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.06944: Col #189=+HACTIVEDISPLAY
00:18:22:46.06944: Col #190=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.07072: Col #191=+HACTIVEDISPLAY
00:18:22:46.07200: Col #192=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.07200: Col #193=+HACTIVEDISPLAY
00:18:22:46.07328: Col #194=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.07456: Col #195=+HACTIVEDISPLAY
00:18:22:46.07456: Col #196=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.07584: Col #197=+HACTIVEDISPLAY
00:18:22:46.07712: Col #198=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.07712: Col #199=+HACTIVEDISPLAY
00:18:22:46.07840: Col #200=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.07968: Col #201=+HACTIVEDISPLAY
00:18:22:46.07968: Col #202=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08096: Col #203=+HACTIVEDISPLAY
00:18:22:46.08096: Col #204=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08224: Col #205=+HACTIVEDISPLAY
00:18:22:46.08352: Col #206=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08480: Col #207=+HACTIVEDISPLAY
00:18:22:46.08480: Col #208=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.08608: Col #209=+HACTIVEDISPLAY
00:18:22:46.08608: Col #210=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08736: Col #211=+HACTIVEDISPLAY
00:18:22:46.08864: Col #212=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08992: Col #213=+HACTIVEDISPLAY
00:18:22:46.08992: Col #214=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.08992: Col #215=+HACTIVEDISPLAY
00:18:22:46.09120: Col #216=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:46.09248: Col #217=+HACTIVEDISPLAY
00:18:22:46.09376: Col #218=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.09504: Col #219=+HACTIVEDISPLAY
00:18:22:46.09504: Col #220=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.09504: Col #221=+HACTIVEDISPLAY
00:18:22:46.09632: Col #222=+HACTIVEDISPLAY+WRITEBACK
00:18:22:46.09760: Col #223=+HACTIVEDISPLAY
00:18:22:46.09888: Col #224=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.00016: Col #225=+HACTIVEDISPLAY
00:18:22:47.00016: Col #226=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.00016: Col #227=+HACTIVEDISPLAY
00:18:22:47.00144: Col #228=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.00272: Col #229=+HACTIVEDISPLAY
00:18:22:47.00400: Col #230=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.00400: Col #231=+HACTIVEDISPLAY
00:18:22:47.00528: Col #232=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.00528: Col #233=+HACTIVEDISPLAY
00:18:22:47.00656: Col #234=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.00784: Col #235=+HACTIVEDISPLAY
00:18:22:47.00912: Col #236=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.00912: Col #237=+HACTIVEDISPLAY
00:18:22:47.01040: Col #238=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.01040: Col #239=+HACTIVEDISPLAY
00:18:22:47.01296: Col #240=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.01424: Col #241=+HACTIVEDISPLAY
00:18:22:47.01424: Col #242=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.01552: Col #243=+HACTIVEDISPLAY
00:18:22:47.01552: Col #244=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.01680: Col #245=+HACTIVEDISPLAY
00:18:22:47.01808: Col #246=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.01808: Col #247=+HACTIVEDISPLAY
00:18:22:47.01936: Col #248=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.02064: Col #249=+HACTIVEDISPLAY
00:18:22:47.02064: Col #250=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.02192: Col #251=+HACTIVEDISPLAY
00:18:22:47.02320: Col #252=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.02320: Col #253=+HACTIVEDISPLAY
00:18:22:47.02448: Col #254=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.02576: Col #255=+HACTIVEDISPLAY
00:18:22:47.02576: Col #256=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.02704: Col #257=+HACTIVEDISPLAY
00:18:22:47.02704: Col #258=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.02832: Col #259=+HACTIVEDISPLAY
00:18:22:47.02960: Col #260=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.03088: Col #261=+HACTIVEDISPLAY
00:18:22:47.03088: Col #262=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.03216: Col #263=+HACTIVEDISPLAY
00:18:22:47.03216: Col #264=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.03344: Col #265=+HACTIVEDISPLAY
00:18:22:47.03472: Col #266=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.03600: Col #267=+HACTIVEDISPLAY
00:18:22:47.03600: Col #268=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.03728: Col #269=+HACTIVEDISPLAY
00:18:22:47.03728: Col #270=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.03856: Col #271=+HACTIVEDISPLAY
00:18:22:47.03984: Col #272=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.04112: Col #273=+HACTIVEDISPLAY
00:18:22:47.04112: Col #274=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.04240: Col #275=+HACTIVEDISPLAY
00:18:22:47.04368: Col #276=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.04496: Col #277=+HACTIVEDISPLAY
00:18:22:47.04624: Col #278=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.04624: Col #279=+HACTIVEDISPLAY
00:18:22:47.04752: Col #280=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.04752: Col #281=+HACTIVEDISPLAY
00:18:22:47.04880: Col #282=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.05008: Col #283=+HACTIVEDISPLAY
00:18:22:47.05136: Col #284=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.05136: Col #285=+HACTIVEDISPLAY
00:18:22:47.05264: Col #286=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.05392: Col #287=+HACTIVEDISPLAY
00:18:22:47.05392: Col #288=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.05520: Col #289=+HACTIVEDISPLAY
00:18:22:47.05648: Col #290=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.05648: Col #291=+HACTIVEDISPLAY
00:18:22:47.05776: Col #292=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.05904: Col #293=+HACTIVEDISPLAY
00:18:22:47.05904: Col #294=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.06032: Col #295=+HACTIVEDISPLAY
00:18:22:47.06160: Col #296=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.06160: Col #297=+HACTIVEDISPLAY
00:18:22:47.06288: Col #298=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.06288: Col #299=+HACTIVEDISPLAY
00:18:22:47.06416: Col #300=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.06544: Col #301=+HACTIVEDISPLAY
00:18:22:47.06672: Col #302=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.06672: Col #303=+HACTIVEDISPLAY
00:18:22:47.06800: Col #304=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.06800: Col #305=+HACTIVEDISPLAY
00:18:22:47.06928: Col #306=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.07056: Col #307=+HACTIVEDISPLAY
00:18:22:47.07184: Col #308=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.07184: Col #309=+HACTIVEDISPLAY
00:18:22:47.07184: Col #310=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.07312: Col #311=+HACTIVEDISPLAY
00:18:22:47.07440: Col #312=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.07568: Col #313=+HACTIVEDISPLAY
00:18:22:47.07696: Col #314=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.07696: Col #315=+HACTIVEDISPLAY
00:18:22:47.07824: Col #316=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.07952: Col #317=+HACTIVEDISPLAY
00:18:22:47.08080: Col #318=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.08080: Col #319=+HACTIVEDISPLAY
00:18:22:47.08208: Col #320=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.08208: Col #321=+HACTIVEDISPLAY
00:18:22:47.08336: Col #322=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.08464: Col #323=+HACTIVEDISPLAY
00:18:22:47.08592: Col #324=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.08592: Col #325=+HACTIVEDISPLAY
00:18:22:47.08720: Col #326=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.08720: Col #327=+HACTIVEDISPLAY
00:18:22:47.08848: Col #328=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.08976: Col #329=+HACTIVEDISPLAY
00:18:22:47.08976: Col #330=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.09104: Col #331=+HACTIVEDISPLAY
00:18:22:47.09232: Col #332=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.09232: Col #333=+HACTIVEDISPLAY
00:18:22:47.09360: Col #334=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.09488: Col #335=+HACTIVEDISPLAY
00:18:22:47.09488: Col #336=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:47.09616: Col #337=+HACTIVEDISPLAY
00:18:22:47.09744: Col #338=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.09744: Col #339=+HACTIVEDISPLAY
00:18:22:47.09872: Col #340=+HACTIVEDISPLAY+WRITEBACK
00:18:22:47.09872: Col #341=+HACTIVEDISPLAY
00:18:22:48.00000: Col #342=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.00128: Col #343=+HACTIVEDISPLAY
00:18:22:48.00256: Col #344=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.00256: Col #345=+HACTIVEDISPLAY
00:18:22:48.00384: Col #346=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.00384: Col #347=+HACTIVEDISPLAY
00:18:22:48.00512: Col #348=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.00640: Col #349=+HACTIVEDISPLAY
00:18:22:48.00768: Col #350=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.00768: Col #351=+HACTIVEDISPLAY
00:18:22:48.00768: Col #352=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.00896: Col #353=+HACTIVEDISPLAY
00:18:22:48.01024: Col #354=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.01152: Col #355=+HACTIVEDISPLAY
00:18:22:48.01280: Col #356=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.01280: Col #357=+HACTIVEDISPLAY
00:18:22:48.01280: Col #358=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.01408: Col #359=+HACTIVEDISPLAY
00:18:22:48.01536: Col #360=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.01664: Col #361=+HACTIVEDISPLAY
00:18:22:48.01792: Col #362=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.01792: Col #363=+HACTIVEDISPLAY
00:18:22:48.01792: Col #364=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.01920: Col #365=+HACTIVEDISPLAY
00:18:22:48.02048: Col #366=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.02176: Col #367=+HACTIVEDISPLAY
00:18:22:48.02304: Col #368=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.02304: Col #369=+HACTIVEDISPLAY
00:18:22:48.02304: Col #370=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.02432: Col #371=+HACTIVEDISPLAY
00:18:22:48.02560: Col #372=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.02688: Col #373=+HACTIVEDISPLAY
00:18:22:48.02688: Col #374=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.02816: Col #375=+HACTIVEDISPLAY
00:18:22:48.02816: Col #376=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.02944: Col #377=+HACTIVEDISPLAY
00:18:22:48.03072: Col #378=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.03200: Col #379=+HACTIVEDISPLAY
00:18:22:48.03200: Col #380=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.03328: Col #381=+HACTIVEDISPLAY
00:18:22:48.03328: Col #382=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.03456: Col #383=+HACTIVEDISPLAY
00:18:22:48.03584: Col #384=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.03712: Col #385=+HACTIVEDISPLAY
00:18:22:48.03712: Col #386=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.03840: Col #387=+HACTIVEDISPLAY
00:18:22:48.03840: Col #388=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.03968: Col #389=+HACTIVEDISPLAY
00:18:22:48.04096: Col #390=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.04096: Col #391=+HACTIVEDISPLAY
00:18:22:48.04224: Col #392=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.04352: Col #393=+HACTIVEDISPLAY
00:18:22:48.04352: Col #394=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.04480: Col #395=+HACTIVEDISPLAY
00:18:22:48.04608: Col #396=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.04608: Col #397=+HACTIVEDISPLAY
00:18:22:48.04736: Col #398=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.04864: Col #399=+HACTIVEDISPLAY
00:18:22:48.04864: Col #400=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.04992: Col #401=+HACTIVEDISPLAY
00:18:22:48.04992: Col #402=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.05120: Col #403=+HACTIVEDISPLAY
00:18:22:48.05248: Col #404=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.05376: Col #405=+HACTIVEDISPLAY
00:18:22:48.05376: Col #406=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.05504: Col #407=+HACTIVEDISPLAY
00:18:22:48.05504: Col #408=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.05632: Col #409=+HACTIVEDISPLAY
00:18:22:48.05760: Col #410=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.05888: Col #411=+HACTIVEDISPLAY
00:18:22:48.05888: Col #412=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.05888: Col #413=+HACTIVEDISPLAY
00:18:22:48.06016: Col #414=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.06144: Col #415=+HACTIVEDISPLAY
00:18:22:48.06272: Col #416=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.06400: Col #417=+HACTIVEDISPLAY
00:18:22:48.06400: Col #418=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.06400: Col #419=+HACTIVEDISPLAY
00:18:22:48.06528: Col #420=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.06656: Col #421=+HACTIVEDISPLAY
00:18:22:48.06784: Col #422=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.06912: Col #423=+HACTIVEDISPLAY
00:18:22:48.06912: Col #424=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.06912: Col #425=+HACTIVEDISPLAY
00:18:22:48.07040: Col #426=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.07168: Col #427=+HACTIVEDISPLAY
00:18:22:48.07296: Col #428=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.07424: Col #429=+HACTIVEDISPLAY
00:18:22:48.07424: Col #430=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.07424: Col #431=+HACTIVEDISPLAY
00:18:22:48.07552: Col #432=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.07680: Col #433=+HACTIVEDISPLAY
00:18:22:48.07808: Col #434=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.07808: Col #435=+HACTIVEDISPLAY
00:18:22:48.07936: Col #436=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.07936: Col #437=+HACTIVEDISPLAY
00:18:22:48.08064: Col #438=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.08192: Col #439=+HACTIVEDISPLAY
00:18:22:48.08320: Col #440=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.08320: Col #441=+HACTIVEDISPLAY
00:18:22:48.08448: Col #442=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.08448: Col #443=+HACTIVEDISPLAY
00:18:22:48.08576: Col #444=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.08704: Col #445=+HACTIVEDISPLAY
00:18:22:48.08704: Col #446=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.08832: Col #447=+HACTIVEDISPLAY
00:18:22:48.08960: Col #448=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.08960: Col #449=+HACTIVEDISPLAY
00:18:22:48.09088: Col #450=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.09216: Col #451=+HACTIVEDISPLAY
00:18:22:48.09216: Col #452=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.09344: Col #453=+HACTIVEDISPLAY
00:18:22:48.09472: Col #454=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.09472: Col #455=+HACTIVEDISPLAY
00:18:22:48.09600: Col #456=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:48.09600: Col #457=+HACTIVEDISPLAY
00:18:22:48.09728: Col #458=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.09856: Col #459=+HACTIVEDISPLAY
00:18:22:48.09984: Col #460=+HACTIVEDISPLAY+WRITEBACK
00:18:22:48.09984: Col #461=+HACTIVEDISPLAY
00:18:22:49.00112: Col #462=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.00112: Col #463=+HACTIVEDISPLAY
00:18:22:49.00240: Col #464=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.00368: Col #465=+HACTIVEDISPLAY
00:18:22:49.00496: Col #466=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.00496: Col #467=+HACTIVEDISPLAY
00:18:22:49.00624: Col #468=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.00624: Col #469=+HACTIVEDISPLAY
00:18:22:49.00752: Col #470=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.00880: Col #471=+HACTIVEDISPLAY
00:18:22:49.01008: Col #472=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.01008: Col #473=+HACTIVEDISPLAY
00:18:22:49.01008: Col #474=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.01136: Col #475=+HACTIVEDISPLAY
00:18:22:49.01264: Col #476=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.01392: Col #477=+HACTIVEDISPLAY
00:18:22:49.01520: Col #478=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.01520: Col #479=+HACTIVEDISPLAY
00:18:22:49.01520: Col #480=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.01648: Col #481=+HACTIVEDISPLAY
00:18:22:49.01776: Col #482=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.01904: Col #483=+HACTIVEDISPLAY
00:18:22:49.02032: Col #484=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.02032: Col #485=+HACTIVEDISPLAY
00:18:22:49.02032: Col #486=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.02160: Col #487=+HACTIVEDISPLAY
00:18:22:49.02288: Col #488=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.02416: Col #489=+HACTIVEDISPLAY
00:18:22:49.02544: Col #490=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.02544: Col #491=+HACTIVEDISPLAY
00:18:22:49.02544: Col #492=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.02672: Col #493=+HACTIVEDISPLAY
00:18:22:49.02800: Col #494=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.02928: Col #495=+HACTIVEDISPLAY
00:18:22:49.03056: Col #496=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.03056: Col #497=+HACTIVEDISPLAY
00:18:22:49.03056: Col #498=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.03184: Col #499=+HACTIVEDISPLAY
00:18:22:49.03312: Col #500=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.03440: Col #501=+HACTIVEDISPLAY
00:18:22:49.03440: Col #502=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.03568: Col #503=+HACTIVEDISPLAY
00:18:22:49.03568: Col #504=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.03696: Col #505=+HACTIVEDISPLAY
00:18:22:49.03824: Col #506=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.03952: Col #507=+HACTIVEDISPLAY
00:18:22:49.04080: Col #508=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.04080: Col #509=+HACTIVEDISPLAY
00:18:22:49.04080: Col #510=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.04208: Col #511=+HACTIVEDISPLAY
00:18:22:49.04336: Col #512=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.04464: Col #513=+HACTIVEDISPLAY
00:18:22:49.04464: Col #514=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.04592: Col #515=+HACTIVEDISPLAY
00:18:22:49.04592: Col #516=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.04720: Col #517=+HACTIVEDISPLAY
00:18:22:49.04848: Col #518=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.04976: Col #519=+HACTIVEDISPLAY
00:18:22:49.04976: Col #520=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.05104: Col #521=+HACTIVEDISPLAY
00:18:22:49.05104: Col #522=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.05232: Col #523=+HACTIVEDISPLAY
00:18:22:49.05360: Col #524=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.05360: Col #525=+HACTIVEDISPLAY
00:18:22:49.05488: Col #526=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.05616: Col #527=+HACTIVEDISPLAY
00:18:22:49.05616: Col #528=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.05744: Col #529=+HACTIVEDISPLAY
00:18:22:49.05872: Col #530=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.05872: Col #531=+HACTIVEDISPLAY
00:18:22:49.06000: Col #532=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.06128: Col #533=+HACTIVEDISPLAY
00:18:22:49.06128: Col #534=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.06256: Col #535=+HACTIVEDISPLAY
00:18:22:49.06384: Col #536=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.06384: Col #537=+HACTIVEDISPLAY
00:18:22:49.06512: Col #538=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.06640: Col #539=+HACTIVEDISPLAY
00:18:22:49.06640: Col #540=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.06768: Col #541=+HACTIVEDISPLAY
00:18:22:49.06768: Col #542=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.06896: Col #543=+HACTIVEDISPLAY
00:18:22:49.07024: Col #544=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.07152: Col #545=+HACTIVEDISPLAY
00:18:22:49.07152: Col #546=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.07280: Col #547=+HACTIVEDISPLAY
00:18:22:49.07280: Col #548=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.07408: Col #549=+HACTIVEDISPLAY
00:18:22:49.07536: Col #550=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.07664: Col #551=+HACTIVEDISPLAY
00:18:22:49.07664: Col #552=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.07664: Col #553=+HACTIVEDISPLAY
00:18:22:49.07792: Col #554=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.07920: Col #555=+HACTIVEDISPLAY
00:18:22:49.08048: Col #556=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.08176: Col #557=+HACTIVEDISPLAY
00:18:22:49.08176: Col #558=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.08176: Col #559=+HACTIVEDISPLAY
00:18:22:49.08304: Col #560=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.08432: Col #561=+HACTIVEDISPLAY
00:18:22:49.08560: Col #562=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.08688: Col #563=+HACTIVEDISPLAY
00:18:22:49.08688: Col #564=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.08688: Col #565=+HACTIVEDISPLAY
00:18:22:49.08816: Col #566=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.08944: Col #567=+HACTIVEDISPLAY
00:18:22:49.09072: Col #568=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.09200: Col #569=+HACTIVEDISPLAY
00:18:22:49.09200: Col #570=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.09200: Col #571=+HACTIVEDISPLAY
00:18:22:49.09328: Col #572=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.09456: Col #573=+HACTIVEDISPLAY
00:18:22:49.09584: Col #574=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.09712: Col #575=+HACTIVEDISPLAY
00:18:22:49.09712: Col #576=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:49.09712: Col #577=+HACTIVEDISPLAY
00:18:22:49.09840: Col #578=+HACTIVEDISPLAY+WRITEBACK
00:18:22:49.09968: Col #579=+HACTIVEDISPLAY
00:18:22:50.00096: Col #580=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.00096: Col #581=+HACTIVEDISPLAY
00:18:22:50.00224: Col #582=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.00224: Col #583=+HACTIVEDISPLAY
00:18:22:50.00352: Col #584=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.00480: Col #585=+HACTIVEDISPLAY
00:18:22:50.00608: Col #586=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.00608: Col #587=+HACTIVEDISPLAY
00:18:22:50.00736: Col #588=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.00736: Col #589=+HACTIVEDISPLAY
00:18:22:50.00864: Col #590=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.00992: Col #591=+HACTIVEDISPLAY
00:18:22:50.00992: Col #592=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.01120: Col #593=+HACTIVEDISPLAY
00:18:22:50.01248: Col #594=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.01248: Col #595=+HACTIVEDISPLAY
00:18:22:50.01376: Col #596=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.01504: Col #597=+HACTIVEDISPLAY
00:18:22:50.01504: Col #598=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.01632: Col #599=+HACTIVEDISPLAY
00:18:22:50.01760: Col #600=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.01760: Col #601=+HACTIVEDISPLAY
00:18:22:50.01888: Col #602=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.01888: Col #603=+HACTIVEDISPLAY
00:18:22:50.02016: Col #604=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.02144: Col #605=+HACTIVEDISPLAY
00:18:22:50.02272: Col #606=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.02272: Col #607=+HACTIVEDISPLAY
00:18:22:50.02400: Col #608=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.02400: Col #609=+HACTIVEDISPLAY
00:18:22:50.02528: Col #610=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.02656: Col #611=+HACTIVEDISPLAY
00:18:22:50.02784: Col #612=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.02784: Col #613=+HACTIVEDISPLAY
00:18:22:50.02784: Col #614=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.02912: Col #615=+HACTIVEDISPLAY
00:18:22:50.03040: Col #616=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.03168: Col #617=+HACTIVEDISPLAY
00:18:22:50.03296: Col #618=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.03296: Col #619=+HACTIVEDISPLAY
00:18:22:50.03296: Col #620=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.03424: Col #621=+HACTIVEDISPLAY
00:18:22:50.03552: Col #622=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.03680: Col #623=+HACTIVEDISPLAY
00:18:22:50.03808: Col #624=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.03808: Col #625=+HACTIVEDISPLAY
00:18:22:50.03808: Col #626=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.03936: Col #627=+HACTIVEDISPLAY
00:18:22:50.04064: Col #628=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.04192: Col #629=+HACTIVEDISPLAY
00:18:22:50.04320: Col #630=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.04320: Col #631=+HACTIVEDISPLAY
00:18:22:50.04320: Col #632=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:18:22:50.04448: Col #633=+HACTIVEDISPLAY
00:18:22:50.04576: Col #634=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.04704: Col #635=+HACTIVEDISPLAY
00:18:22:50.04704: Col #636=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.04832: Col #637=+HACTIVEDISPLAY
00:18:22:50.04832: Col #638=+HACTIVEDISPLAY+WRITEBACK
00:18:22:50.04960: Col #639=+HACTIVEDISPLAY
00:18:22:50.05088: Col #640=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.05216: Col #641=+OVERSCAN
00:18:22:50.05344: Col #642=+OVERSCAN+WRITEBACK
00:18:22:50.05344: Col #643=+OVERSCAN
00:18:22:50.05344: Col #644=+OVERSCAN+WRITEBACK
00:18:22:50.05472: Col #645=+OVERSCAN
00:18:22:50.05600: Col #646=+OVERSCAN+WRITEBACK
00:18:22:50.05728: Col #647=+OVERSCAN
00:18:22:50.05856: Col #648=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.05856: Col #649=+OVERSCAN
00:18:22:50.05856: Col #650=+OVERSCAN+WRITEBACK
00:18:22:50.05984: Col #651=+OVERSCAN
00:18:22:50.06112: Col #652=+OVERSCAN+WRITEBACK
00:18:22:50.06240: Col #653=+OVERSCAN
00:18:22:50.06368: Col #654=+OVERSCAN+WRITEBACK
00:18:22:50.06368: Col #655=+OVERSCAN
00:18:22:50.06368: Col #656=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.06496: Col #657=+OVERSCAN
00:18:22:50.06624: Col #658=+OVERSCAN+WRITEBACK
00:18:22:50.06752: Col #659=+OVERSCAN
00:18:22:50.06752: Col #660=+OVERSCAN+WRITEBACK
00:18:22:50.06880: Col #661=+OVERSCAN
00:18:22:50.06880: Col #662=+OVERSCAN+WRITEBACK
00:18:22:50.07008: Col #663=+OVERSCAN
00:18:22:50.07136: Col #664=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.07264: Col #665=+OVERSCAN
00:18:22:50.07264: Col #666=+OVERSCAN+WRITEBACK
00:18:22:50.07392: Col #667=+OVERSCAN
00:18:22:50.07392: Col #668=+OVERSCAN+WRITEBACK
00:18:22:50.07520: Col #669=+OVERSCAN
00:18:22:50.07648: Col #670=+OVERSCAN+WRITEBACK
00:18:22:50.07648: Col #671=+OVERSCAN
00:18:22:50.07776: Col #672=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.07904: Col #673=+OVERSCAN
00:18:22:50.07904: Col #674=+OVERSCAN+WRITEBACK
00:18:22:50.08032: Col #675=+OVERSCAN
00:18:22:50.08032: Col #676=+OVERSCAN+WRITEBACK
00:18:22:50.08160: Col #677=+OVERSCAN
00:18:22:50.08288: Col #678=+OVERSCAN+WRITEBACK
00:18:22:50.08416: Col #679=+OVERSCAN
00:18:22:50.08416: Col #680=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.08544: Col #681=+OVERSCAN
00:18:22:50.08544: Col #682=+OVERSCAN+WRITEBACK
00:18:22:50.08672: Col #683=+OVERSCAN
00:18:22:50.08800: Col #684=+OVERSCAN+WRITEBACK
00:18:22:50.08928: Col #685=+OVERSCAN
00:18:22:50.08928: Col #686=+OVERSCAN+WRITEBACK
00:18:22:50.08928: Col #687=+OVERSCAN
00:18:22:50.09056: Col #688=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.09184: Col #689=+OVERSCAN
00:18:22:50.09312: Col #690=+OVERSCAN+WRITEBACK
00:18:22:50.09440: Col #691=+OVERSCAN
00:18:22:50.09440: Col #692=+OVERSCAN+WRITEBACK
00:18:22:50.09568: Col #693=+OVERSCAN
00:18:22:50.09696: Col #694=+OVERSCAN+WRITEBACK
00:18:22:50.09824: Col #695=+OVERSCAN
00:18:22:50.09824: Col #696=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:50.09952: Col #697=+OVERSCAN
00:18:22:50.09952: Col #698=+OVERSCAN+WRITEBACK
00:18:22:51.00080: Col #699=+OVERSCAN
00:18:22:51.00208: Col #700=+OVERSCAN+WRITEBACK
00:18:22:51.00336: Col #701=+OVERSCAN
00:18:22:51.00336: Col #702=+OVERSCAN+WRITEBACK
00:18:22:51.00464: Col #703=+OVERSCAN
00:18:22:51.00464: Col #704=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.00592: Col #705=+OVERSCAN
00:18:22:51.00720: Col #706=+OVERSCAN+WRITEBACK
00:18:22:51.00720: Col #707=+OVERSCAN
00:18:22:51.00848: Col #708=+OVERSCAN+WRITEBACK
00:18:22:51.00976: Col #709=+OVERSCAN
00:18:22:51.00976: Col #710=+OVERSCAN+WRITEBACK
00:18:22:51.01104: Col #711=+OVERSCAN
00:18:22:51.01232: Col #712=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.01232: Col #713=+OVERSCAN
00:18:22:51.01360: Col #714=+OVERSCAN+WRITEBACK
00:18:22:51.01488: Col #715=+OVERSCAN
00:18:22:51.01488: Col #716=+OVERSCAN+WRITEBACK
00:18:22:51.01616: Col #717=+OVERSCAN
00:18:22:51.01616: Col #718=+OVERSCAN+WRITEBACK
00:18:22:51.01744: Col #719=+OVERSCAN
00:18:22:51.01872: Col #720=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.02000: Col #721=+HRETRACESTART+OVERSCAN
00:18:22:51.02000: Col #722=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.02128: Col #723=+HRETRACESTART+OVERSCAN
00:18:22:51.02128: Col #724=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.02256: Col #725=+HRETRACESTART+OVERSCAN
00:18:22:51.02384: Col #726=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.02512: Col #727=+HRETRACESTART+OVERSCAN
00:18:22:51.02512: Col #728=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.02640: Col #729=+HRETRACESTART+OVERSCAN
00:18:22:51.02640: Col #730=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.02768: Col #731=+HRETRACESTART+OVERSCAN
00:18:22:51.02896: Col #732=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.03024: Col #733=+HRETRACESTART+OVERSCAN
00:18:22:51.03024: Col #734=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.03024: Col #735=+HRETRACESTART+OVERSCAN
00:18:22:51.03152: Col #736=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.03280: Col #737=+HRETRACESTART+OVERSCAN
00:18:22:51.03408: Col #738=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.03536: Col #739=+HRETRACESTART+OVERSCAN
00:18:22:51.03536: Col #740=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.03536: Col #741=+HRETRACESTART+OVERSCAN
00:18:22:51.03664: Col #742=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.03792: Col #743=+HRETRACESTART+OVERSCAN
00:18:22:51.03920: Col #744=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.04048: Col #745=+HRETRACESTART+OVERSCAN
00:18:22:51.04048: Col #746=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.04048: Col #747=+HRETRACESTART+OVERSCAN
00:18:22:51.04176: Col #748=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.04304: Col #749=+HRETRACESTART+OVERSCAN
00:18:22:51.04432: Col #750=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.04560: Col #751=+HRETRACESTART+OVERSCAN
00:18:22:51.04560: Col #752=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.04560: Col #753=+HRETRACESTART+OVERSCAN
00:18:22:51.04688: Col #754=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.04816: Col #755=+HRETRACESTART+OVERSCAN
00:18:22:51.04944: Col #756=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.05072: Col #757=+HRETRACESTART+OVERSCAN
00:18:22:51.05072: Col #758=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.05072: Col #759=+HRETRACESTART+OVERSCAN
00:18:22:51.05200: Col #760=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.05328: Col #761=+HRETRACESTART+OVERSCAN
00:18:22:51.05456: Col #762=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.05584: Col #763=+HRETRACESTART+OVERSCAN
00:18:22:51.05584: Col #764=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.05584: Col #765=+HRETRACESTART+OVERSCAN
00:18:22:51.05712: Col #766=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.05840: Col #767=+HRETRACESTART+OVERSCAN
00:18:22:51.05968: Col #768=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.06096: Col #769=+HRETRACESTART+OVERSCAN
00:18:22:51.06096: Col #770=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.06096: Col #771=+HRETRACESTART+OVERSCAN
00:18:22:51.06224: Col #772=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.06352: Col #773=+HRETRACESTART+OVERSCAN
00:18:22:51.06480: Col #774=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.06608: Col #775=+HRETRACESTART+OVERSCAN
00:18:22:51.06608: Col #776=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.06608: Col #777=+HRETRACESTART+OVERSCAN
00:18:22:51.06736: Col #778=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.06864: Col #779=+HRETRACESTART+OVERSCAN
00:18:22:51.06992: Col #780=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.07120: Col #781=+HRETRACESTART+OVERSCAN
00:18:22:51.07120: Col #782=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.07120: Col #783=+HRETRACESTART+OVERSCAN
00:18:22:51.07248: Col #784=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.07376: Col #785=+HRETRACESTART+OVERSCAN
00:18:22:51.07504: Col #786=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.07632: Col #787=+HRETRACESTART+OVERSCAN
00:18:22:51.07632: Col #788=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.07760: Col #789=+HRETRACESTART+OVERSCAN
00:18:22:51.07760: Col #790=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.07888: Col #791=+HRETRACESTART+OVERSCAN
00:18:22:51.08016: Col #792=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.08144: Col #793=+HRETRACESTART+OVERSCAN
00:18:22:51.08144: Col #794=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.08272: Col #795=+HRETRACESTART+OVERSCAN
00:18:22:51.08272: Col #796=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.08400: Col #797=+HRETRACESTART+OVERSCAN
00:18:22:51.08528: Col #798=+HRETRACESTART+OVERSCAN+WRITEBACK
00:18:22:51.08656: Col #799=+HRETRACESTART+OVERSCAN
00:18:22:51.08656: Col #800=+HRETRACEEND+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.08784: Col #801=+HRETRACEEND+OVERSCAN
00:18:22:51.08784: Col #802=+OVERSCAN+WRITEBACK
00:18:22:51.08912: Col #803=+OVERSCAN
00:18:22:51.09040: Col #804=+OVERSCAN+WRITEBACK
00:18:22:51.09168: Col #805=+OVERSCAN
00:18:22:51.09168: Col #806=+OVERSCAN+WRITEBACK
00:18:22:51.09168: Col #807=+OVERSCAN
00:18:22:51.09296: Col #808=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:51.09424: Col #809=+OVERSCAN
00:18:22:51.09552: Col #810=+OVERSCAN+WRITEBACK
00:18:22:51.09680: Col #811=+OVERSCAN
00:18:22:51.09680: Col #812=+OVERSCAN+WRITEBACK
00:18:22:51.09680: Col #813=+OVERSCAN
00:18:22:51.09808: Col #814=+OVERSCAN+WRITEBACK
00:18:22:51.09936: Col #815=+OVERSCAN
00:18:22:52.00064: Col #816=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.00192: Col #817=+OVERSCAN
00:18:22:52.00192: Col #818=+OVERSCAN+WRITEBACK
00:18:22:52.00192: Col #819=+OVERSCAN
00:18:22:52.00320: Col #820=+OVERSCAN+WRITEBACK
00:18:22:52.00448: Col #821=+OVERSCAN
00:18:22:52.00576: Col #822=+OVERSCAN+WRITEBACK
00:18:22:52.00576: Col #823=+OVERSCAN
00:18:22:52.00704: Col #824=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.00704: Col #825=+OVERSCAN
00:18:22:52.00832: Col #826=+OVERSCAN+WRITEBACK
00:18:22:52.00960: Col #827=+OVERSCAN
00:18:22:52.00960: Col #828=+OVERSCAN+WRITEBACK
00:18:22:52.01088: Col #829=+OVERSCAN
00:18:22:52.01216: Col #830=+OVERSCAN+WRITEBACK
00:18:22:52.01216: Col #831=+OVERSCAN
00:18:22:52.01344: Col #832=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.01472: Col #833=+OVERSCAN
00:18:22:52.01472: Col #834=+OVERSCAN+WRITEBACK
00:18:22:52.01600: Col #835=+OVERSCAN
00:18:22:52.01728: Col #836=+OVERSCAN+WRITEBACK
00:18:22:52.01728: Col #837=+OVERSCAN
00:18:22:52.01856: Col #838=+OVERSCAN+WRITEBACK
00:18:22:52.01856: Col #839=+OVERSCAN
00:18:22:52.01984: Col #840=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.02112: Col #841=+OVERSCAN
00:18:22:52.02240: Col #842=+OVERSCAN+WRITEBACK
00:18:22:52.02240: Col #843=+OVERSCAN
00:18:22:52.02240: Col #844=+OVERSCAN+WRITEBACK
00:18:22:52.02368: Col #845=+OVERSCAN
00:18:22:52.02496: Col #846=+OVERSCAN+WRITEBACK
00:18:22:52.02624: Col #847=+OVERSCAN
00:18:22:52.02752: Col #848=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.02752: Col #849=+OVERSCAN
00:18:22:52.02752: Col #850=+OVERSCAN+WRITEBACK
00:18:22:52.02880: Col #851=+OVERSCAN
00:18:22:52.03008: Col #852=+OVERSCAN+WRITEBACK
00:18:22:52.03136: Col #853=+OVERSCAN
00:18:22:52.03264: Col #854=+OVERSCAN+WRITEBACK
00:18:22:52.03264: Col #855=+OVERSCAN
00:18:22:52.03264: Col #856=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.03392: Col #857=+OVERSCAN
00:18:22:52.03520: Col #858=+OVERSCAN+WRITEBACK
00:18:22:52.03648: Col #859=+OVERSCAN
00:18:22:52.03776: Col #860=+OVERSCAN+WRITEBACK
00:18:22:52.03776: Col #861=+OVERSCAN
00:18:22:52.03776: Col #862=+OVERSCAN+WRITEBACK
00:18:22:52.03904: Col #863=+OVERSCAN
00:18:22:52.04032: Col #864=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.04160: Col #865=+OVERSCAN
00:18:22:52.04288: Col #866=+OVERSCAN+WRITEBACK
00:18:22:52.04288: Col #867=+OVERSCAN
00:18:22:52.04288: Col #868=+OVERSCAN+WRITEBACK
00:18:22:52.04416: Col #869=+OVERSCAN
00:18:22:52.04544: Col #870=+OVERSCAN+WRITEBACK
00:18:22:52.04672: Col #871=+OVERSCAN
00:18:22:52.04800: Col #872=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.04800: Col #873=+OVERSCAN
00:18:22:52.04800: Col #874=+OVERSCAN+WRITEBACK
00:18:22:52.04928: Col #875=+OVERSCAN
00:18:22:52.05056: Col #876=+OVERSCAN+WRITEBACK
00:18:22:52.05184: Col #877=+OVERSCAN
00:18:22:52.05312: Col #878=+OVERSCAN+WRITEBACK
00:18:22:52.05312: Col #879=+OVERSCAN
00:18:22:52.05440: Col #880=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.05440: Col #881=+OVERSCAN
00:18:22:52.05568: Col #882=+OVERSCAN+WRITEBACK
00:18:22:52.05696: Col #883=+OVERSCAN
00:18:22:52.05824: Col #884=+OVERSCAN+WRITEBACK
00:18:22:52.05824: Col #885=+OVERSCAN
00:18:22:52.05952: Col #886=+OVERSCAN+WRITEBACK
00:18:22:52.05952: Col #887=+OVERSCAN
00:18:22:52.06080: Col #888=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.06208: Col #889=+OVERSCAN
00:18:22:52.06336: Col #890=+OVERSCAN+WRITEBACK
00:18:22:52.06336: Col #891=+OVERSCAN
00:18:22:52.06336: Col #892=+OVERSCAN+WRITEBACK
00:18:22:52.06464: Col #893=+OVERSCAN
00:18:22:52.06592: Col #894=+OVERSCAN+WRITEBACK
00:18:22:52.06720: Col #895=+OVERSCAN
00:18:22:52.06848: Col #896=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.06848: Col #897=+OVERSCAN
00:18:22:52.06848: Col #898=+OVERSCAN+WRITEBACK
00:18:22:52.06976: Col #899=+OVERSCAN
00:18:22:52.07104: Col #900=+OVERSCAN+WRITEBACK
00:18:22:52.07232: Col #901=+OVERSCAN
00:18:22:52.07360: Col #902=+OVERSCAN+WRITEBACK
00:18:22:52.07360: Col #903=+OVERSCAN
00:18:22:52.07360: Col #904=+OVERSCAN+WRITEBACK+HALFCLOCK
00:18:22:52.07488: Col #905=+OVERSCAN
00:18:22:52.07616: Col #906=+OVERSCAN+WRITEBACK
00:18:22:52.07744: Col #907=+OVERSCAN
00:18:22:52.07744: Col #908=+OVERSCAN+WRITEBACK
00:18:22:52.07872: Col #909=+OVERSCAN
00:18:22:52.07872: Col #910=+OVERSCAN+WRITEBACK
00:18:22:52.08000: Col #911=+OVERSCAN
00:18:22:52.08128: Col #912=+HTOTAL+OVERSCAN+HSYNCRESET+WRITEBACK+HALFCLOCK

The VGA.log also contains some other information, but that is unused in CGA/MDA graphics cards (they are precalc values based on the VGA renderer, whose aren't used in the CGA timings and not loaded by the emulator for usage on the MC6845 emulation).

Horizontal timings look fine (writeback every other clock due to half pixel timing. Every 2nd halfclock is a reload from VRAM (it's only used every halfclock in certain SVGA scenarios). The first halfclock on Col #0 isn't present because it's done on HTotal instead (together with initializing the horizontal counters, which is done on the same clock as Col #0, since HTotal immediately moves to Col #0's timing and executes it on the same clock cycle)) and vertical timings seem to be a single scanline, which should be fine too.
The interesting thing is then the vertical timings, which is probably where it messes up? I see that every 2nd scanline is the exact same as the first scanline after all? The fonts look pretty messed up.

A screen capture of it:

33-UniPCemu_CGA_COMP_vertical timing issue.png
Filename
33-UniPCemu_CGA_COMP_vertical timing issue.png
File size
14.18 KiB
Views
883 views
File comment
CGA COMP vertical timing issue.
File license
Fair use/fair dealing exception

Edit: Hmmm... UniPCemu essentially flips the MAP13 counter (which selects even and odd fields) every horizontal total, but vertical total always clears the counter. Since there's only 1 horizontal total in such a single-scanline frame, it never gets to rendering odd fields and thus renders even fields only on every scanline?

Anyone knows how a real CGA handles that? When does the flipflop of a MAP13 odd/even field get cleared?
Edit: Oddly enough, during the "Which CGA am I?" screen, in both applications, I only see the start address changing after every 2 scanlines? That probably shouldn't be happening?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 49 of 122, by superfury

User metadata
Rank l33t++
Rank
l33t++

Is reengine listening? Perhaps he knows what might be going wrong here?
Or perhaps Trixter?

Edit: Managed to fixed the vertical total issue.

The way the vertical total was applied was a bit wrong:

	if (row>VGA->registers->CGARegistersMasked[4]) //Past total specified?
{
if (!((((VGA->registers->CGARegistersMasked[4]+1)*charheight)+VGA->registers->CGARegistersMasked[5])<=y)) //Vertical total adjustment reaced?
{
result |= VGA_SIGNAL_VTOTAL; //End of display: start the next frame!
result |= VGA_SIGNAL_VSYNCRESET; //Reset VSync!
}
}

Should have been:

	if (row>VGA->registers->CGARegistersMasked[4]) //Past total specified?
{
if (((((VGA->registers->CGARegistersMasked[4]+1)*charheight)+VGA->registers->CGARegistersMasked[5])<=y)) //Vertical total adjustment reaced?
{
result |= VGA_SIGNAL_VTOTAL; //End of display: start the next frame!
result |= VGA_SIGNAL_VSYNCRESET; //Reset VSync!
}
}
	if (row>VGA->registers->CGARegistersMasked[4]) //Past total specified?
{
if (((((VGA->registers->CGARegistersMasked[4]+1)*charheight)+VGA->registers->CGARegistersMasked[5])<=y)) //Vertical total adjustment reaced?
{
result |= VGA_SIGNAL_VTOTAL; //End of display: start the next frame!
result |= VGA_SIGNAL_VSYNCRESET; //Reset VSync!
}
}

Edit: OK. The CGA in UniPCemu is now properly rendering 2 scanlines per frame on the racing the beam part. Still it's never actually rendering overscan? It's rendering 912 clocks per scanline.

Edit: Horizontal and vertical timings during the 42th scanline on the screen:

UniPCemu's single row timings during the Racing the beam effect
00:35:39:57.03248: Row #0=+VRETRACEEND+VBLANKEND+VACTIVEDISPLAY
00:35:39:57.04912: Row #1=+VACTIVEDISPLAY
00:35:39:57.05296: Row #2=+VTOTAL+OVERSCAN+VSYNCRESET
00:35:39:57.05296: Col #0=+HRETRACEEND+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.05552: Col #1=+HRETRACEEND+HACTIVEDISPLAY
00:35:39:57.05680: Col #2=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.05680: Col #3=+HACTIVEDISPLAY
00:35:39:57.05936: Col #4=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.06192: Col #5=+HACTIVEDISPLAY
00:35:39:57.06320: Col #6=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.06576: Col #7=+HACTIVEDISPLAY
00:35:39:57.06704: Col #8=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:57.06960: Col #9=+HACTIVEDISPLAY
00:35:39:57.06960: Col #10=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.07216: Col #11=+HACTIVEDISPLAY
00:35:39:57.07728: Col #12=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.07728: Col #13=+HACTIVEDISPLAY
00:35:39:57.07984: Col #14=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.07984: Col #15=+HACTIVEDISPLAY
00:35:39:57.08240: Col #16=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:57.08240: Col #17=+HACTIVEDISPLAY
00:35:39:57.08240: Col #18=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.08368: Col #19=+HACTIVEDISPLAY
00:35:39:57.08624: Col #20=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.08624: Col #21=+HACTIVEDISPLAY
00:35:39:57.08752: Col #22=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.09008: Col #23=+HACTIVEDISPLAY
00:35:39:57.09008: Col #24=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:57.09008: Col #25=+HACTIVEDISPLAY
00:35:39:57.09264: Col #26=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.09264: Col #27=+HACTIVEDISPLAY
00:35:39:57.09392: Col #28=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.09648: Col #29=+HACTIVEDISPLAY
00:35:39:57.09648: Col #30=+HACTIVEDISPLAY+WRITEBACK
00:35:39:57.09776: Col #31=+HACTIVEDISPLAY
00:35:39:58.00032: Col #32=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.00032: Col #33=+HACTIVEDISPLAY
00:35:39:58.00288: Col #34=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.00288: Col #35=+HACTIVEDISPLAY
00:35:39:58.00416: Col #36=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.00416: Col #37=+HACTIVEDISPLAY
00:35:39:58.00672: Col #38=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.00672: Col #39=+HACTIVEDISPLAY
00:35:39:58.00800: Col #40=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.00800: Col #41=+HACTIVEDISPLAY
00:35:39:58.01056: Col #42=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.01056: Col #43=+HACTIVEDISPLAY
00:35:39:58.01312: Col #44=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.01312: Col #45=+HACTIVEDISPLAY
00:35:39:58.01440: Col #46=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.01696: Col #47=+HACTIVEDISPLAY
00:35:39:58.01696: Col #48=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.01824: Col #49=+HACTIVEDISPLAY
00:35:39:58.02080: Col #50=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.02080: Col #51=+HACTIVEDISPLAY
00:35:39:58.02336: Col #52=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.02336: Col #53=+HACTIVEDISPLAY
00:35:39:58.02464: Col #54=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.02464: Col #55=+HACTIVEDISPLAY
00:35:39:58.02720: Col #56=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
Show last 856 lines
00:35:39:58.02720: Col #57=+HACTIVEDISPLAY
00:35:39:58.02848: Col #58=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.03104: Col #59=+HACTIVEDISPLAY
00:35:39:58.03360: Col #60=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.03488: Col #61=+HACTIVEDISPLAY
00:35:39:58.03488: Col #62=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.03744: Col #63=+HACTIVEDISPLAY
00:35:39:58.03744: Col #64=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.03872: Col #65=+HACTIVEDISPLAY
00:35:39:58.03872: Col #66=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.04128: Col #67=+HACTIVEDISPLAY
00:35:39:58.04128: Col #68=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.04384: Col #69=+HACTIVEDISPLAY
00:35:39:58.04512: Col #70=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.04512: Col #71=+HACTIVEDISPLAY
00:35:39:58.04768: Col #72=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.04768: Col #73=+HACTIVEDISPLAY
00:35:39:58.04896: Col #74=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.04896: Col #75=+HACTIVEDISPLAY
00:35:39:58.05152: Col #76=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.05152: Col #77=+HACTIVEDISPLAY
00:35:39:58.05408: Col #78=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.05536: Col #79=+HACTIVEDISPLAY
00:35:39:58.05536: Col #80=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.05792: Col #81=+HACTIVEDISPLAY
00:35:39:58.05792: Col #82=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.05920: Col #83=+HACTIVEDISPLAY
00:35:39:58.06176: Col #84=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.06176: Col #85=+HACTIVEDISPLAY
00:35:39:58.06432: Col #86=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.06560: Col #87=+HACTIVEDISPLAY
00:35:39:58.06560: Col #88=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.06816: Col #89=+HACTIVEDISPLAY
00:35:39:58.06816: Col #90=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.06944: Col #91=+HACTIVEDISPLAY
00:35:39:58.06944: Col #92=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.07200: Col #93=+HACTIVEDISPLAY
00:35:39:58.07200: Col #94=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.07456: Col #95=+HACTIVEDISPLAY
00:35:39:58.07456: Col #96=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.07584: Col #97=+HACTIVEDISPLAY
00:35:39:58.07584: Col #98=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.07840: Col #99=+HACTIVEDISPLAY
00:35:39:58.07968: Col #100=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.07968: Col #101=+HACTIVEDISPLAY
00:35:39:58.08224: Col #102=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.08480: Col #103=+HACTIVEDISPLAY
00:35:39:58.08480: Col #104=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.08608: Col #105=+HACTIVEDISPLAY
00:35:39:58.08864: Col #106=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.08864: Col #107=+HACTIVEDISPLAY
00:35:39:58.08992: Col #108=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.08992: Col #109=+HACTIVEDISPLAY
00:35:39:58.08992: Col #110=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.09248: Col #111=+HACTIVEDISPLAY
00:35:39:58.09248: Col #112=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:58.09504: Col #113=+HACTIVEDISPLAY
00:35:39:58.09504: Col #114=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.09632: Col #115=+HACTIVEDISPLAY
00:35:39:58.09632: Col #116=+HACTIVEDISPLAY+WRITEBACK
00:35:39:58.09888: Col #117=+HACTIVEDISPLAY
00:35:39:59.00272: Col #118=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.00272: Col #119=+HACTIVEDISPLAY
00:35:39:59.00528: Col #120=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.00656: Col #121=+HACTIVEDISPLAY
00:35:39:59.00912: Col #122=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.00912: Col #123=+HACTIVEDISPLAY
00:35:39:59.01040: Col #124=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.01296: Col #125=+HACTIVEDISPLAY
00:35:39:59.01296: Col #126=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.01552: Col #127=+HACTIVEDISPLAY
00:35:39:59.01552: Col #128=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.01680: Col #129=+HACTIVEDISPLAY
00:35:39:59.01936: Col #130=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.01936: Col #131=+HACTIVEDISPLAY
00:35:39:59.02064: Col #132=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.02064: Col #133=+HACTIVEDISPLAY
00:35:39:59.02320: Col #134=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.02576: Col #135=+HACTIVEDISPLAY
00:35:39:59.02704: Col #136=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.02704: Col #137=+HACTIVEDISPLAY
00:35:39:59.02960: Col #138=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.02960: Col #139=+HACTIVEDISPLAY
00:35:39:59.03088: Col #140=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.03088: Col #141=+HACTIVEDISPLAY
00:35:39:59.03344: Col #142=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.03344: Col #143=+HACTIVEDISPLAY
00:35:39:59.03600: Col #144=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.03600: Col #145=+HACTIVEDISPLAY
00:35:39:59.03728: Col #146=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.03984: Col #147=+HACTIVEDISPLAY
00:35:39:59.03984: Col #148=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.04112: Col #149=+HACTIVEDISPLAY
00:35:39:59.04112: Col #150=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.04368: Col #151=+HACTIVEDISPLAY
00:35:39:59.04368: Col #152=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.04624: Col #153=+HACTIVEDISPLAY
00:35:39:59.04624: Col #154=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.04752: Col #155=+HACTIVEDISPLAY
00:35:39:59.04752: Col #156=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.04752: Col #157=+HACTIVEDISPLAY
00:35:39:59.05008: Col #158=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.05136: Col #159=+HACTIVEDISPLAY
00:35:39:59.05136: Col #160=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.05392: Col #161=+HACTIVEDISPLAY
00:35:39:59.05392: Col #162=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.05648: Col #163=+HACTIVEDISPLAY
00:35:39:59.05776: Col #164=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.05776: Col #165=+HACTIVEDISPLAY
00:35:39:59.06032: Col #166=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.06160: Col #167=+HACTIVEDISPLAY
00:35:39:59.06160: Col #168=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.06416: Col #169=+HACTIVEDISPLAY
00:35:39:59.06672: Col #170=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.06672: Col #171=+HACTIVEDISPLAY
00:35:39:59.06800: Col #172=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.06800: Col #173=+HACTIVEDISPLAY
00:35:39:59.07056: Col #174=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.07056: Col #175=+HACTIVEDISPLAY
00:35:39:59.07184: Col #176=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.07184: Col #177=+HACTIVEDISPLAY
00:35:39:59.07440: Col #178=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.07440: Col #179=+HACTIVEDISPLAY
00:35:39:59.07696: Col #180=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.07696: Col #181=+HACTIVEDISPLAY
00:35:39:59.07824: Col #182=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.07824: Col #183=+HACTIVEDISPLAY
00:35:39:59.08080: Col #184=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.08080: Col #185=+HACTIVEDISPLAY
00:35:39:59.08208: Col #186=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.08464: Col #187=+HACTIVEDISPLAY
00:35:39:59.08464: Col #188=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.08720: Col #189=+HACTIVEDISPLAY
00:35:39:59.08848: Col #190=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.08848: Col #191=+HACTIVEDISPLAY
00:35:39:59.09104: Col #192=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:59.09232: Col #193=+HACTIVEDISPLAY
00:35:39:59.09232: Col #194=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.09488: Col #195=+HACTIVEDISPLAY
00:35:39:59.09744: Col #196=+HACTIVEDISPLAY+WRITEBACK
00:35:39:59.09872: Col #197=+HACTIVEDISPLAY
00:35:39:59.09872: Col #198=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.00128: Col #199=+HACTIVEDISPLAY
00:35:39:60.00128: Col #200=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.00256: Col #201=+HACTIVEDISPLAY
00:35:39:60.00256: Col #202=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.00512: Col #203=+HACTIVEDISPLAY
00:35:39:60.00512: Col #204=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.00768: Col #205=+HACTIVEDISPLAY
00:35:39:60.00896: Col #206=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.01152: Col #207=+HACTIVEDISPLAY
00:35:39:60.01280: Col #208=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.01536: Col #209=+HACTIVEDISPLAY
00:35:39:60.01792: Col #210=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.01792: Col #211=+HACTIVEDISPLAY
00:35:39:60.01920: Col #212=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.02176: Col #213=+HACTIVEDISPLAY
00:35:39:60.02176: Col #214=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.02304: Col #215=+HACTIVEDISPLAY
00:35:39:60.02560: Col #216=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.02560: Col #217=+HACTIVEDISPLAY
00:35:39:60.02816: Col #218=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.02816: Col #219=+HACTIVEDISPLAY
00:35:39:60.02944: Col #220=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.02944: Col #221=+HACTIVEDISPLAY
00:35:39:60.03200: Col #222=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.03200: Col #223=+HACTIVEDISPLAY
00:35:39:60.03328: Col #224=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.03328: Col #225=+HACTIVEDISPLAY
00:35:39:60.03584: Col #226=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.03584: Col #227=+HACTIVEDISPLAY
00:35:39:60.03840: Col #228=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.03840: Col #229=+HACTIVEDISPLAY
00:35:39:60.03968: Col #230=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.04224: Col #231=+HACTIVEDISPLAY
00:35:39:60.04352: Col #232=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.04608: Col #233=+HACTIVEDISPLAY
00:35:39:60.04608: Col #234=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.04864: Col #235=+HACTIVEDISPLAY
00:35:39:60.04992: Col #236=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.05248: Col #237=+HACTIVEDISPLAY
00:35:39:60.05248: Col #238=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.05376: Col #239=+HACTIVEDISPLAY
00:35:39:60.05376: Col #240=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.05632: Col #241=+HACTIVEDISPLAY
00:35:39:60.05632: Col #242=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.05888: Col #243=+HACTIVEDISPLAY
00:35:39:60.05888: Col #244=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.06016: Col #245=+HACTIVEDISPLAY
00:35:39:60.06016: Col #246=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.06272: Col #247=+HACTIVEDISPLAY
00:35:39:60.06272: Col #248=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.06400: Col #249=+HACTIVEDISPLAY
00:35:39:60.06400: Col #250=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.06656: Col #251=+HACTIVEDISPLAY
00:35:39:60.06656: Col #252=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.06912: Col #253=+HACTIVEDISPLAY
00:35:39:60.06912: Col #254=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.07040: Col #255=+HACTIVEDISPLAY
00:35:39:60.07040: Col #256=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.07296: Col #257=+HACTIVEDISPLAY
00:35:39:60.07296: Col #258=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.07424: Col #259=+HACTIVEDISPLAY
00:35:39:60.07680: Col #260=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.07680: Col #261=+HACTIVEDISPLAY
00:35:39:60.07936: Col #262=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.08064: Col #263=+HACTIVEDISPLAY
00:35:39:60.08064: Col #264=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.08320: Col #265=+HACTIVEDISPLAY
00:35:39:60.08320: Col #266=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.08448: Col #267=+HACTIVEDISPLAY
00:35:39:60.08704: Col #268=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.08704: Col #269=+HACTIVEDISPLAY
00:35:39:60.08960: Col #270=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.08960: Col #271=+HACTIVEDISPLAY
00:35:39:60.09088: Col #272=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:60.09088: Col #273=+HACTIVEDISPLAY
00:35:39:60.09344: Col #274=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.09344: Col #275=+HACTIVEDISPLAY
00:35:39:60.09472: Col #276=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.09728: Col #277=+HACTIVEDISPLAY
00:35:39:60.09728: Col #278=+HACTIVEDISPLAY+WRITEBACK
00:35:39:60.09984: Col #279=+HACTIVEDISPLAY
00:35:39:60.09984: Col #280=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.00112: Col #281=+HACTIVEDISPLAY
00:35:39:61.00368: Col #282=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.00368: Col #283=+HACTIVEDISPLAY
00:35:39:61.00496: Col #284=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.00496: Col #285=+HACTIVEDISPLAY
00:35:39:61.00752: Col #286=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.00752: Col #287=+HACTIVEDISPLAY
00:35:39:61.01008: Col #288=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.01008: Col #289=+HACTIVEDISPLAY
00:35:39:61.01136: Col #290=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.01136: Col #291=+HACTIVEDISPLAY
00:35:39:61.01392: Col #292=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.01392: Col #293=+HACTIVEDISPLAY
00:35:39:61.01520: Col #294=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.01520: Col #295=+HACTIVEDISPLAY
00:35:39:61.01776: Col #296=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.01776: Col #297=+HACTIVEDISPLAY
00:35:39:61.02032: Col #298=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.02032: Col #299=+HACTIVEDISPLAY
00:35:39:61.02160: Col #300=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.02160: Col #301=+HACTIVEDISPLAY
00:35:39:61.02416: Col #302=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.02416: Col #303=+HACTIVEDISPLAY
00:35:39:61.02544: Col #304=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.02544: Col #305=+HACTIVEDISPLAY
00:35:39:61.02800: Col #306=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.02800: Col #307=+HACTIVEDISPLAY
00:35:39:61.03056: Col #308=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.03056: Col #309=+HACTIVEDISPLAY
00:35:39:61.03184: Col #310=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.03184: Col #311=+HACTIVEDISPLAY
00:35:39:61.03440: Col #312=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.03440: Col #313=+HACTIVEDISPLAY
00:35:39:61.03568: Col #314=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.03568: Col #315=+HACTIVEDISPLAY
00:35:39:61.03824: Col #316=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.03824: Col #317=+HACTIVEDISPLAY
00:35:39:61.04080: Col #318=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.04080: Col #319=+HACTIVEDISPLAY
00:35:39:61.04208: Col #320=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.04464: Col #321=+HACTIVEDISPLAY
00:35:39:61.04464: Col #322=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.04592: Col #323=+HACTIVEDISPLAY
00:35:39:61.04592: Col #324=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.04848: Col #325=+HACTIVEDISPLAY
00:35:39:61.04848: Col #326=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.05104: Col #327=+HACTIVEDISPLAY
00:35:39:61.05232: Col #328=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.05232: Col #329=+HACTIVEDISPLAY
00:35:39:61.05488: Col #330=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.05488: Col #331=+HACTIVEDISPLAY
00:35:39:61.05616: Col #332=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.05616: Col #333=+HACTIVEDISPLAY
00:35:39:61.05872: Col #334=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.06128: Col #335=+HACTIVEDISPLAY
00:35:39:61.06128: Col #336=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.06256: Col #337=+HACTIVEDISPLAY
00:35:39:61.06256: Col #338=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.06512: Col #339=+HACTIVEDISPLAY
00:35:39:61.06640: Col #340=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.06640: Col #341=+HACTIVEDISPLAY
00:35:39:61.06896: Col #342=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.07152: Col #343=+HACTIVEDISPLAY
00:35:39:61.07152: Col #344=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.07280: Col #345=+HACTIVEDISPLAY
00:35:39:61.07280: Col #346=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.07536: Col #347=+HACTIVEDISPLAY
00:35:39:61.07664: Col #348=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.07664: Col #349=+HACTIVEDISPLAY
00:35:39:61.07920: Col #350=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.08176: Col #351=+HACTIVEDISPLAY
00:35:39:61.08176: Col #352=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.08304: Col #353=+HACTIVEDISPLAY
00:35:39:61.08560: Col #354=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.08688: Col #355=+HACTIVEDISPLAY
00:35:39:61.08688: Col #356=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.08944: Col #357=+HACTIVEDISPLAY
00:35:39:61.08944: Col #358=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.09200: Col #359=+HACTIVEDISPLAY
00:35:39:61.09200: Col #360=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:61.09328: Col #361=+HACTIVEDISPLAY
00:35:39:61.09328: Col #362=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.09584: Col #363=+HACTIVEDISPLAY
00:35:39:61.09584: Col #364=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.09712: Col #365=+HACTIVEDISPLAY
00:35:39:61.09712: Col #366=+HACTIVEDISPLAY+WRITEBACK
00:35:39:61.09968: Col #367=+HACTIVEDISPLAY
00:35:39:61.09968: Col #368=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.00224: Col #369=+HACTIVEDISPLAY
00:35:39:62.00224: Col #370=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.00352: Col #371=+HACTIVEDISPLAY
00:35:39:62.00352: Col #372=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.00608: Col #373=+HACTIVEDISPLAY
00:35:39:62.00608: Col #374=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.00736: Col #375=+HACTIVEDISPLAY
00:35:39:62.00736: Col #376=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.00992: Col #377=+HACTIVEDISPLAY
00:35:39:62.00992: Col #378=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.01248: Col #379=+HACTIVEDISPLAY
00:35:39:62.01248: Col #380=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.01248: Col #381=+HACTIVEDISPLAY
00:35:39:62.01376: Col #382=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.01376: Col #383=+HACTIVEDISPLAY
00:35:39:62.01632: Col #384=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.01632: Col #385=+HACTIVEDISPLAY
00:35:39:62.01760: Col #386=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.01760: Col #387=+HACTIVEDISPLAY
00:35:39:62.02016: Col #388=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.02016: Col #389=+HACTIVEDISPLAY
00:35:39:62.02272: Col #390=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.02272: Col #391=+HACTIVEDISPLAY
00:35:39:62.02400: Col #392=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.02400: Col #393=+HACTIVEDISPLAY
00:35:39:62.02656: Col #394=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.02656: Col #395=+HACTIVEDISPLAY
00:35:39:62.02656: Col #396=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.02784: Col #397=+HACTIVEDISPLAY
00:35:39:62.02784: Col #398=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.03040: Col #399=+HACTIVEDISPLAY
00:35:39:62.03296: Col #400=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.03296: Col #401=+HACTIVEDISPLAY
00:35:39:62.03424: Col #402=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.03424: Col #403=+HACTIVEDISPLAY
00:35:39:62.03680: Col #404=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.03680: Col #405=+HACTIVEDISPLAY
00:35:39:62.03808: Col #406=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.03808: Col #407=+HACTIVEDISPLAY
00:35:39:62.04064: Col #408=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.04064: Col #409=+HACTIVEDISPLAY
00:35:39:62.04320: Col #410=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.04320: Col #411=+HACTIVEDISPLAY
00:35:39:62.04448: Col #412=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.04448: Col #413=+HACTIVEDISPLAY
00:35:39:62.04704: Col #414=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.04704: Col #415=+HACTIVEDISPLAY
00:35:39:62.04832: Col #416=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.04832: Col #417=+HACTIVEDISPLAY
00:35:39:62.05088: Col #418=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.05088: Col #419=+HACTIVEDISPLAY
00:35:39:62.05344: Col #420=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.05344: Col #421=+HACTIVEDISPLAY
00:35:39:62.05472: Col #422=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.05472: Col #423=+HACTIVEDISPLAY
00:35:39:62.05728: Col #424=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.05728: Col #425=+HACTIVEDISPLAY
00:35:39:62.05856: Col #426=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.05856: Col #427=+HACTIVEDISPLAY
00:35:39:62.06112: Col #428=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.06112: Col #429=+HACTIVEDISPLAY
00:35:39:62.06368: Col #430=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.06368: Col #431=+HACTIVEDISPLAY
00:35:39:62.06496: Col #432=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.06496: Col #433=+HACTIVEDISPLAY
00:35:39:62.06496: Col #434=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.06752: Col #435=+HACTIVEDISPLAY
00:35:39:62.06752: Col #436=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.06880: Col #437=+HACTIVEDISPLAY
00:35:39:62.06880: Col #438=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.07136: Col #439=+HACTIVEDISPLAY
00:35:39:62.07136: Col #440=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.07392: Col #441=+HACTIVEDISPLAY
00:35:39:62.07392: Col #442=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.07520: Col #443=+HACTIVEDISPLAY
00:35:39:62.07520: Col #444=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.07776: Col #445=+HACTIVEDISPLAY
00:35:39:62.07776: Col #446=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.07904: Col #447=+HACTIVEDISPLAY
00:35:39:62.07904: Col #448=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.07904: Col #449=+HACTIVEDISPLAY
00:35:39:62.08160: Col #450=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.08160: Col #451=+HACTIVEDISPLAY
00:35:39:62.08416: Col #452=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.08416: Col #453=+HACTIVEDISPLAY
00:35:39:62.08544: Col #454=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.08544: Col #455=+HACTIVEDISPLAY
00:35:39:62.08800: Col #456=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.08800: Col #457=+HACTIVEDISPLAY
00:35:39:62.08928: Col #458=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.08928: Col #459=+HACTIVEDISPLAY
00:35:39:62.09184: Col #460=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.09184: Col #461=+HACTIVEDISPLAY
00:35:39:62.09440: Col #462=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.09440: Col #463=+HACTIVEDISPLAY
00:35:39:62.09440: Col #464=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:62.09568: Col #465=+HACTIVEDISPLAY
00:35:39:62.09568: Col #466=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.09824: Col #467=+HACTIVEDISPLAY
00:35:39:62.09824: Col #468=+HACTIVEDISPLAY+WRITEBACK
00:35:39:62.09952: Col #469=+HACTIVEDISPLAY
00:35:39:62.09952: Col #470=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.00208: Col #471=+HACTIVEDISPLAY
00:35:39:63.00208: Col #472=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.00464: Col #473=+HACTIVEDISPLAY
00:35:39:63.00464: Col #474=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.00592: Col #475=+HACTIVEDISPLAY
00:35:39:63.00592: Col #476=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.00848: Col #477=+HACTIVEDISPLAY
00:35:39:63.00848: Col #478=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.00976: Col #479=+HACTIVEDISPLAY
00:35:39:63.00976: Col #480=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.00976: Col #481=+HACTIVEDISPLAY
00:35:39:63.01232: Col #482=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.01232: Col #483=+HACTIVEDISPLAY
00:35:39:63.01488: Col #484=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.01488: Col #485=+HACTIVEDISPLAY
00:35:39:63.01616: Col #486=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.01616: Col #487=+HACTIVEDISPLAY
00:35:39:63.01872: Col #488=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.01872: Col #489=+HACTIVEDISPLAY
00:35:39:63.02000: Col #490=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.02000: Col #491=+HACTIVEDISPLAY
00:35:39:63.02256: Col #492=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.02256: Col #493=+HACTIVEDISPLAY
00:35:39:63.02512: Col #494=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.02512: Col #495=+HACTIVEDISPLAY
00:35:39:63.02512: Col #496=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.02640: Col #497=+HACTIVEDISPLAY
00:35:39:63.02640: Col #498=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.02896: Col #499=+HACTIVEDISPLAY
00:35:39:63.02896: Col #500=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.03024: Col #501=+HACTIVEDISPLAY
00:35:39:63.03024: Col #502=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.03280: Col #503=+HACTIVEDISPLAY
00:35:39:63.03280: Col #504=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.03536: Col #505=+HACTIVEDISPLAY
00:35:39:63.03536: Col #506=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.03664: Col #507=+HACTIVEDISPLAY
00:35:39:63.03664: Col #508=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.03920: Col #509=+HACTIVEDISPLAY
00:35:39:63.03920: Col #510=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.03920: Col #511=+HACTIVEDISPLAY
00:35:39:63.04048: Col #512=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.04048: Col #513=+HACTIVEDISPLAY
00:35:39:63.04304: Col #514=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.04304: Col #515=+HACTIVEDISPLAY
00:35:39:63.04560: Col #516=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.04688: Col #517=+HACTIVEDISPLAY
00:35:39:63.04944: Col #518=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.04944: Col #519=+HACTIVEDISPLAY
00:35:39:63.05072: Col #520=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.05328: Col #521=+HACTIVEDISPLAY
00:35:39:63.05328: Col #522=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.05584: Col #523=+HACTIVEDISPLAY
00:35:39:63.05584: Col #524=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.05712: Col #525=+HACTIVEDISPLAY
00:35:39:63.05968: Col #526=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.05968: Col #527=+HACTIVEDISPLAY
00:35:39:63.06096: Col #528=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.06096: Col #529=+HACTIVEDISPLAY
00:35:39:63.06352: Col #530=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.06608: Col #531=+HACTIVEDISPLAY
00:35:39:63.06608: Col #532=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.06736: Col #533=+HACTIVEDISPLAY
00:35:39:63.06736: Col #534=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.06992: Col #535=+HACTIVEDISPLAY
00:35:39:63.07120: Col #536=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.07120: Col #537=+HACTIVEDISPLAY
00:35:39:63.07376: Col #538=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.07632: Col #539=+HACTIVEDISPLAY
00:35:39:63.07632: Col #540=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.07760: Col #541=+HACTIVEDISPLAY
00:35:39:63.08016: Col #542=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.08016: Col #543=+HACTIVEDISPLAY
00:35:39:63.08144: Col #544=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.08144: Col #545=+HACTIVEDISPLAY
00:35:39:63.08400: Col #546=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.08656: Col #547=+HACTIVEDISPLAY
00:35:39:63.08656: Col #548=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.08784: Col #549=+HACTIVEDISPLAY
00:35:39:63.09040: Col #550=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.09040: Col #551=+HACTIVEDISPLAY
00:35:39:63.09168: Col #552=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:63.09168: Col #553=+HACTIVEDISPLAY
00:35:39:63.09424: Col #554=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.09424: Col #555=+HACTIVEDISPLAY
00:35:39:63.09680: Col #556=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.09680: Col #557=+HACTIVEDISPLAY
00:35:39:63.09808: Col #558=+HACTIVEDISPLAY+WRITEBACK
00:35:39:63.09808: Col #559=+HACTIVEDISPLAY
00:35:39:64.00064: Col #560=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.00064: Col #561=+HACTIVEDISPLAY
00:35:39:64.00192: Col #562=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.00192: Col #563=+HACTIVEDISPLAY
00:35:39:64.00448: Col #564=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.00448: Col #565=+HACTIVEDISPLAY
00:35:39:64.00704: Col #566=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.00704: Col #567=+HACTIVEDISPLAY
00:35:39:64.00832: Col #568=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.00832: Col #569=+HACTIVEDISPLAY
00:35:39:64.01088: Col #570=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.01088: Col #571=+HACTIVEDISPLAY
00:35:39:64.01216: Col #572=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.01216: Col #573=+HACTIVEDISPLAY
00:35:39:64.01216: Col #574=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.01472: Col #575=+HACTIVEDISPLAY
00:35:39:64.01472: Col #576=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.01728: Col #577=+HACTIVEDISPLAY
00:35:39:64.01728: Col #578=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.01856: Col #579=+HACTIVEDISPLAY
00:35:39:64.01856: Col #580=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.02112: Col #581=+HACTIVEDISPLAY
00:35:39:64.02112: Col #582=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.02240: Col #583=+HACTIVEDISPLAY
00:35:39:64.02240: Col #584=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.02496: Col #585=+HACTIVEDISPLAY
00:35:39:64.02496: Col #586=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.02752: Col #587=+HACTIVEDISPLAY
00:35:39:64.02752: Col #588=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.02880: Col #589=+HACTIVEDISPLAY
00:35:39:64.02880: Col #590=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.02880: Col #591=+HACTIVEDISPLAY
00:35:39:64.03136: Col #592=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.03136: Col #593=+HACTIVEDISPLAY
00:35:39:64.03264: Col #594=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.03264: Col #595=+HACTIVEDISPLAY
00:35:39:64.03520: Col #596=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.03520: Col #597=+HACTIVEDISPLAY
00:35:39:64.03776: Col #598=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.03776: Col #599=+HACTIVEDISPLAY
00:35:39:64.03904: Col #600=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.03904: Col #601=+HACTIVEDISPLAY
00:35:39:64.04160: Col #602=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.04160: Col #603=+HACTIVEDISPLAY
00:35:39:64.04288: Col #604=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.04288: Col #605=+HACTIVEDISPLAY
00:35:39:64.04288: Col #606=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.04544: Col #607=+HACTIVEDISPLAY
00:35:39:64.04544: Col #608=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.04800: Col #609=+HACTIVEDISPLAY
00:35:39:64.04800: Col #610=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.04928: Col #611=+HACTIVEDISPLAY
00:35:39:64.04928: Col #612=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.05184: Col #613=+HACTIVEDISPLAY
00:35:39:64.05184: Col #614=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.05312: Col #615=+HACTIVEDISPLAY
00:35:39:64.05312: Col #616=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.05568: Col #617=+HACTIVEDISPLAY
00:35:39:64.05568: Col #618=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.05824: Col #619=+HACTIVEDISPLAY
00:35:39:64.05824: Col #620=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.05824: Col #621=+HACTIVEDISPLAY
00:35:39:64.05952: Col #622=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.05952: Col #623=+HACTIVEDISPLAY
00:35:39:64.06208: Col #624=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.06208: Col #625=+HACTIVEDISPLAY
00:35:39:64.06336: Col #626=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.06336: Col #627=+HACTIVEDISPLAY
00:35:39:64.06592: Col #628=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.06592: Col #629=+HACTIVEDISPLAY
00:35:39:64.06848: Col #630=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.06848: Col #631=+HACTIVEDISPLAY
00:35:39:64.06976: Col #632=+HACTIVEDISPLAY+WRITEBACK+HALFCLOCK
00:35:39:64.06976: Col #633=+HACTIVEDISPLAY
00:35:39:64.07232: Col #634=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.07232: Col #635=+HACTIVEDISPLAY
00:35:39:64.07232: Col #636=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.07360: Col #637=+HACTIVEDISPLAY
00:35:39:64.07360: Col #638=+HACTIVEDISPLAY+WRITEBACK
00:35:39:64.07616: Col #639=+HACTIVEDISPLAY
00:35:39:64.07616: Col #640=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:64.07872: Col #641=+OVERSCAN
00:35:39:64.07872: Col #642=+OVERSCAN+WRITEBACK
00:35:39:64.08000: Col #643=+OVERSCAN
00:35:39:64.08000: Col #644=+OVERSCAN+WRITEBACK
00:35:39:64.08256: Col #645=+OVERSCAN
00:35:39:64.08256: Col #646=+OVERSCAN+WRITEBACK
00:35:39:64.08384: Col #647=+OVERSCAN
00:35:39:64.08384: Col #648=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:64.08640: Col #649=+OVERSCAN
00:35:39:64.08640: Col #650=+OVERSCAN+WRITEBACK
00:35:39:64.08640: Col #651=+OVERSCAN
00:35:39:64.08896: Col #652=+OVERSCAN+WRITEBACK
00:35:39:64.08896: Col #653=+OVERSCAN
00:35:39:64.09024: Col #654=+OVERSCAN+WRITEBACK
00:35:39:64.09024: Col #655=+OVERSCAN
00:35:39:64.09280: Col #656=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:64.09280: Col #657=+OVERSCAN
00:35:39:64.09408: Col #658=+OVERSCAN+WRITEBACK
00:35:39:64.09408: Col #659=+OVERSCAN
00:35:39:64.09664: Col #660=+OVERSCAN+WRITEBACK
00:35:39:64.09664: Col #661=+OVERSCAN
00:35:39:64.09920: Col #662=+OVERSCAN+WRITEBACK
00:35:39:64.09920: Col #663=+OVERSCAN
00:35:39:65.00048: Col #664=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.00048: Col #665=+OVERSCAN
00:35:39:65.00304: Col #666=+OVERSCAN+WRITEBACK
00:35:39:65.00304: Col #667=+OVERSCAN
00:35:39:65.00432: Col #668=+OVERSCAN+WRITEBACK
00:35:39:65.00432: Col #669=+OVERSCAN
00:35:39:65.00688: Col #670=+OVERSCAN+WRITEBACK
00:35:39:65.00688: Col #671=+OVERSCAN
00:35:39:65.00944: Col #672=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.00944: Col #673=+OVERSCAN
00:35:39:65.00944: Col #674=+OVERSCAN+WRITEBACK
00:35:39:65.01072: Col #675=+OVERSCAN
00:35:39:65.01072: Col #676=+OVERSCAN+WRITEBACK
00:35:39:65.01328: Col #677=+OVERSCAN
00:35:39:65.01328: Col #678=+OVERSCAN+WRITEBACK
00:35:39:65.01456: Col #679=+OVERSCAN
00:35:39:65.01456: Col #680=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.01712: Col #681=+OVERSCAN
00:35:39:65.01712: Col #682=+OVERSCAN+WRITEBACK
00:35:39:65.01968: Col #683=+OVERSCAN
00:35:39:65.01968: Col #684=+OVERSCAN+WRITEBACK
00:35:39:65.02096: Col #685=+OVERSCAN
00:35:39:65.02096: Col #686=+OVERSCAN+WRITEBACK
00:35:39:65.02352: Col #687=+OVERSCAN
00:35:39:65.02352: Col #688=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.02352: Col #689=+OVERSCAN
00:35:39:65.02480: Col #690=+OVERSCAN+WRITEBACK
00:35:39:65.02480: Col #691=+OVERSCAN
00:35:39:65.02736: Col #692=+OVERSCAN+WRITEBACK
00:35:39:65.02736: Col #693=+OVERSCAN
00:35:39:65.02992: Col #694=+OVERSCAN+WRITEBACK
00:35:39:65.02992: Col #695=+OVERSCAN
00:35:39:65.03120: Col #696=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.03120: Col #697=+OVERSCAN
00:35:39:65.03376: Col #698=+OVERSCAN+WRITEBACK
00:35:39:65.03376: Col #699=+OVERSCAN
00:35:39:65.03504: Col #700=+OVERSCAN+WRITEBACK
00:35:39:65.03504: Col #701=+OVERSCAN
00:35:39:65.03504: Col #702=+OVERSCAN+WRITEBACK
00:35:39:65.03760: Col #703=+OVERSCAN
00:35:39:65.03760: Col #704=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.04016: Col #705=+OVERSCAN
00:35:39:65.04016: Col #706=+OVERSCAN+WRITEBACK
00:35:39:65.04144: Col #707=+OVERSCAN
00:35:39:65.04144: Col #708=+OVERSCAN+WRITEBACK
00:35:39:65.04400: Col #709=+OVERSCAN
00:35:39:65.04400: Col #710=+OVERSCAN+WRITEBACK
00:35:39:65.04528: Col #711=+OVERSCAN
00:35:39:65.04528: Col #712=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.04784: Col #713=+OVERSCAN
00:35:39:65.04784: Col #714=+OVERSCAN+WRITEBACK
00:35:39:65.05040: Col #715=+OVERSCAN
00:35:39:65.05040: Col #716=+OVERSCAN+WRITEBACK
00:35:39:65.05040: Col #717=+OVERSCAN
00:35:39:65.05168: Col #718=+OVERSCAN+WRITEBACK
00:35:39:65.05168: Col #719=+OVERSCAN
00:35:39:65.05424: Col #720=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.05424: Col #721=+HRETRACESTART+OVERSCAN
00:35:39:65.05552: Col #722=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.05552: Col #723=+HRETRACESTART+OVERSCAN
00:35:39:65.05808: Col #724=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.05808: Col #725=+HRETRACESTART+OVERSCAN
00:35:39:65.06064: Col #726=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.06064: Col #727=+HRETRACESTART+OVERSCAN
00:35:39:65.06192: Col #728=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.06192: Col #729=+HRETRACESTART+OVERSCAN
00:35:39:65.06448: Col #730=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.06448: Col #731=+HRETRACESTART+OVERSCAN
00:35:39:65.06576: Col #732=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.06576: Col #733=+HRETRACESTART+OVERSCAN
00:35:39:65.06576: Col #734=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.06832: Col #735=+HRETRACESTART+OVERSCAN
00:35:39:65.06832: Col #736=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.07088: Col #737=+HRETRACESTART+OVERSCAN
00:35:39:65.07088: Col #738=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.07216: Col #739=+HRETRACESTART+OVERSCAN
00:35:39:65.07216: Col #740=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.07472: Col #741=+HRETRACESTART+OVERSCAN
00:35:39:65.07472: Col #742=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.07600: Col #743=+HRETRACESTART+OVERSCAN
00:35:39:65.07600: Col #744=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.07856: Col #745=+HRETRACESTART+OVERSCAN
00:35:39:65.07856: Col #746=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.08112: Col #747=+HRETRACESTART+OVERSCAN
00:35:39:65.08112: Col #748=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.08240: Col #749=+HRETRACESTART+OVERSCAN
00:35:39:65.08240: Col #750=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.08496: Col #751=+HRETRACESTART+OVERSCAN
00:35:39:65.08496: Col #752=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.08624: Col #753=+HRETRACESTART+OVERSCAN
00:35:39:65.08624: Col #754=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.08880: Col #755=+HRETRACESTART+OVERSCAN
00:35:39:65.08880: Col #756=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.09136: Col #757=+HRETRACESTART+OVERSCAN
00:35:39:65.09136: Col #758=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.09264: Col #759=+HRETRACESTART+OVERSCAN
00:35:39:65.09264: Col #760=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:65.09264: Col #761=+HRETRACESTART+OVERSCAN
00:35:39:65.09520: Col #762=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.09520: Col #763=+HRETRACESTART+OVERSCAN
00:35:39:65.09648: Col #764=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.09648: Col #765=+HRETRACESTART+OVERSCAN
00:35:39:65.09904: Col #766=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:65.09904: Col #767=+HRETRACESTART+OVERSCAN
00:35:39:66.00160: Col #768=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.00160: Col #769=+HRETRACESTART+OVERSCAN
00:35:39:66.00288: Col #770=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.00288: Col #771=+HRETRACESTART+OVERSCAN
00:35:39:66.00544: Col #772=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.00544: Col #773=+HRETRACESTART+OVERSCAN
00:35:39:66.00672: Col #774=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.00672: Col #775=+HRETRACESTART+OVERSCAN
00:35:39:66.00928: Col #776=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.00928: Col #777=+HRETRACESTART+OVERSCAN
00:35:39:66.00928: Col #778=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.01184: Col #779=+HRETRACESTART+OVERSCAN
00:35:39:66.01184: Col #780=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.01312: Col #781=+HRETRACESTART+OVERSCAN
00:35:39:66.01312: Col #782=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.01568: Col #783=+HRETRACESTART+OVERSCAN
00:35:39:66.01568: Col #784=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.01696: Col #785=+HRETRACESTART+OVERSCAN
00:35:39:66.01696: Col #786=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.01952: Col #787=+HRETRACESTART+OVERSCAN
00:35:39:66.01952: Col #788=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.02208: Col #789=+HRETRACESTART+OVERSCAN
00:35:39:66.02208: Col #790=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.02336: Col #791=+HRETRACESTART+OVERSCAN
00:35:39:66.02336: Col #792=+HRETRACESTART+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.02592: Col #793=+HRETRACESTART+OVERSCAN
00:35:39:66.02592: Col #794=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.02592: Col #795=+HRETRACESTART+OVERSCAN
00:35:39:66.02720: Col #796=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.02720: Col #797=+HRETRACESTART+OVERSCAN
00:35:39:66.02976: Col #798=+HRETRACESTART+OVERSCAN+WRITEBACK
00:35:39:66.02976: Col #799=+HRETRACESTART+OVERSCAN
00:35:39:66.03232: Col #800=+HRETRACEEND+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.03232: Col #801=+HRETRACEEND+OVERSCAN
00:35:39:66.03360: Col #802=+OVERSCAN+WRITEBACK
00:35:39:66.03360: Col #803=+OVERSCAN
00:35:39:66.03616: Col #804=+OVERSCAN+WRITEBACK
00:35:39:66.03616: Col #805=+OVERSCAN
00:35:39:66.03744: Col #806=+OVERSCAN+WRITEBACK
00:35:39:66.03744: Col #807=+OVERSCAN
00:35:39:66.04000: Col #808=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.04000: Col #809=+OVERSCAN
00:35:39:66.04000: Col #810=+OVERSCAN+WRITEBACK
00:35:39:66.04256: Col #811=+OVERSCAN
00:35:39:66.04256: Col #812=+OVERSCAN+WRITEBACK
00:35:39:66.04384: Col #813=+OVERSCAN
00:35:39:66.04384: Col #814=+OVERSCAN+WRITEBACK
00:35:39:66.04640: Col #815=+OVERSCAN
00:35:39:66.04640: Col #816=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.04768: Col #817=+OVERSCAN
00:35:39:66.04768: Col #818=+OVERSCAN+WRITEBACK
00:35:39:66.05024: Col #819=+OVERSCAN
00:35:39:66.05024: Col #820=+OVERSCAN+WRITEBACK
00:35:39:66.05280: Col #821=+OVERSCAN
00:35:39:66.05280: Col #822=+OVERSCAN+WRITEBACK
00:35:39:66.05280: Col #823=+OVERSCAN
00:35:39:66.05408: Col #824=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.05408: Col #825=+OVERSCAN
00:35:39:66.05664: Col #826=+OVERSCAN+WRITEBACK
00:35:39:66.05664: Col #827=+OVERSCAN
00:35:39:66.05792: Col #828=+OVERSCAN+WRITEBACK
00:35:39:66.05792: Col #829=+OVERSCAN
00:35:39:66.06048: Col #830=+OVERSCAN+WRITEBACK
00:35:39:66.06048: Col #831=+OVERSCAN
00:35:39:66.06304: Col #832=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.06304: Col #833=+OVERSCAN
00:35:39:66.06432: Col #834=+OVERSCAN+WRITEBACK
00:35:39:66.06432: Col #835=+OVERSCAN
00:35:39:66.06432: Col #836=+OVERSCAN+WRITEBACK
00:35:39:66.06688: Col #837=+OVERSCAN
00:35:39:66.06688: Col #838=+OVERSCAN+WRITEBACK
00:35:39:66.06816: Col #839=+OVERSCAN
00:35:39:66.06816: Col #840=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.07072: Col #841=+OVERSCAN
00:35:39:66.07072: Col #842=+OVERSCAN+WRITEBACK
00:35:39:66.07328: Col #843=+OVERSCAN
00:35:39:66.07328: Col #844=+OVERSCAN+WRITEBACK
00:35:39:66.07328: Col #845=+OVERSCAN
00:35:39:66.07456: Col #846=+OVERSCAN+WRITEBACK
00:35:39:66.07456: Col #847=+OVERSCAN
00:35:39:66.07712: Col #848=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.07712: Col #849=+OVERSCAN
00:35:39:66.07840: Col #850=+OVERSCAN+WRITEBACK
00:35:39:66.07840: Col #851=+OVERSCAN
00:35:39:66.08096: Col #852=+OVERSCAN+WRITEBACK
00:35:39:66.08096: Col #853=+OVERSCAN
00:35:39:66.08096: Col #854=+OVERSCAN+WRITEBACK
00:35:39:66.08352: Col #855=+OVERSCAN
00:35:39:66.08352: Col #856=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.08480: Col #857=+OVERSCAN
00:35:39:66.08480: Col #858=+OVERSCAN+WRITEBACK
00:35:39:66.08736: Col #859=+OVERSCAN
00:35:39:66.08736: Col #860=+OVERSCAN+WRITEBACK
00:35:39:66.08736: Col #861=+OVERSCAN
00:35:39:66.08864: Col #862=+OVERSCAN+WRITEBACK
00:35:39:66.08864: Col #863=+OVERSCAN
00:35:39:66.09120: Col #864=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.09120: Col #865=+OVERSCAN
00:35:39:66.09376: Col #866=+OVERSCAN+WRITEBACK
00:35:39:66.09376: Col #867=+OVERSCAN
00:35:39:66.09504: Col #868=+OVERSCAN+WRITEBACK
00:35:39:66.09504: Col #869=+OVERSCAN
00:35:39:66.09504: Col #870=+OVERSCAN+WRITEBACK
00:35:39:66.09760: Col #871=+OVERSCAN
00:35:39:66.09760: Col #872=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:66.09888: Col #873=+OVERSCAN
00:35:39:66.09888: Col #874=+OVERSCAN+WRITEBACK
00:35:39:67.00144: Col #875=+OVERSCAN
00:35:39:67.00144: Col #876=+OVERSCAN+WRITEBACK
00:35:39:67.00144: Col #877=+OVERSCAN
00:35:39:67.00400: Col #878=+OVERSCAN+WRITEBACK
00:35:39:67.00400: Col #879=+OVERSCAN
00:35:39:67.00528: Col #880=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:67.00528: Col #881=+OVERSCAN
00:35:39:67.00784: Col #882=+OVERSCAN+WRITEBACK
00:35:39:67.00784: Col #883=+OVERSCAN
00:35:39:67.00912: Col #884=+OVERSCAN+WRITEBACK
00:35:39:67.00912: Col #885=+OVERSCAN
00:35:39:67.00912: Col #886=+OVERSCAN+WRITEBACK
00:35:39:67.01168: Col #887=+OVERSCAN
00:35:39:67.01168: Col #888=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:67.01424: Col #889=+OVERSCAN
00:35:39:67.01424: Col #890=+OVERSCAN+WRITEBACK
00:35:39:67.01552: Col #891=+OVERSCAN
00:35:39:67.01552: Col #892=+OVERSCAN+WRITEBACK
00:35:39:67.01552: Col #893=+OVERSCAN
00:35:39:67.01808: Col #894=+OVERSCAN+WRITEBACK
00:35:39:67.01808: Col #895=+OVERSCAN
00:35:39:67.01936: Col #896=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:67.01936: Col #897=+OVERSCAN
00:35:39:67.01936: Col #898=+OVERSCAN+WRITEBACK
00:35:39:67.02192: Col #899=+OVERSCAN
00:35:39:67.02192: Col #900=+OVERSCAN+WRITEBACK
00:35:39:67.02448: Col #901=+OVERSCAN
00:35:39:67.02448: Col #902=+OVERSCAN+WRITEBACK
00:35:39:67.02576: Col #903=+OVERSCAN
00:35:39:67.02576: Col #904=+OVERSCAN+WRITEBACK+HALFCLOCK
00:35:39:67.02576: Col #905=+OVERSCAN
00:35:39:67.02832: Col #906=+OVERSCAN+WRITEBACK
00:35:39:67.02832: Col #907=+OVERSCAN
00:35:39:67.02960: Col #908=+OVERSCAN+WRITEBACK
00:35:39:67.02960: Col #909=+OVERSCAN
00:35:39:67.02960: Col #910=+OVERSCAN+WRITEBACK
00:35:39:67.03216: Col #911=+OVERSCAN
00:35:39:67.03216: Col #912=+HTOTAL+OVERSCAN+HSYNCRESET+WRITEBACK+HALFCLOCK

So 912 clocks per scanline, 2 scanlines per active display.
Edit: Each line is 28h bytes in VRAM (in VGA-compatible VRAM addressing that is). So if you use VGA VRAM addressing instead that's 28*2=50h bytes in linear memory addressed by the CGA. UniPCemu fetches 4 bytes from VRAM instead (50h bytes from planes 0&1 (what CGA can write to) and 50h bytes from planes 2&3 (which aren't writable by the CGA).
UniPCemu transparently remaps memory for CGA by simply writing all VRAM when a memory mode change occurs (it keeps track of what's been written to what CGA VRAM address and performs a full VRAM memory write whenever the VGA-compatible mode changes, clearing all EGA/VGA upper memory planes) to keep the VRAM compatible with the CGA (so the renderer can just read from CGA VRAM in a VGA-compatible way always).

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Reply 50 of 122, by superfury

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Thinking about the movement of the background going wrong, it looks like the position of the solid blocks that appear in the background part of the Kefrens effect follow the motion of the kefrens effect itself? So once the kefrens moves to the right hand side, it keeps moving faster and faster, then once it slows to a halt it moves slower and slower until keeping position for a few frames (only flickering on and off at a constant rate) until the reverse motion happens, which performs in much the same way?

Edit: Area 5150 changed a lot too now:
https://www.dropbox.com/s/yz700sg82mk4guj/Uni … 9-21-29.7z?dl=0

There's a lot of black (or almost fully black) scanlines now, during the cycle-accurate parts?

Last edited by superfury on 2023-07-21, 11:04. Edited 1 time in total.

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Reply 52 of 122, by superfury

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reenigne wrote on 2023-07-21, 07:16:

I'm following the thread but I don't know what the problem is, or even if you've fixed it already.

Well, the intro (the old vs new CGA screen) is fixed now(the bug with vertical total adjust line I mentioned, the code in my last post containing code).

The cycle-accurate parts are still going wrong.

8088 MPH's racing the beam still shows those interesting patterns (see the video I made). It looks like bars (2 scanlines high) of about 4 or 2 clocks being rendered, sometimes both black, sometimes blue, sometimes flipflopping black/blue on frames (producing a flashing/blinking effect). They seem to be moving left and right with the top of the Kefrens effect in the foreground(the sinus effect from top to bottom), which is displayed in a scanline displayed on the first (even) scanline, overscan color on each second (odd) scanline, whose overscan always matches the 'background' that's the same for the entire scanline. Almost like A13 always mapping to zeroed RAM in interlaced graphics modes on the CGA during the effect with a character height of 2(1 stored in the register)? But that might be due to 808x being off a certain fixed amount of clocks on all scanlines?

What I mean with blocks of 2 scanlines high is probably one scanline being rendered in the demo with such a displacement on the raster that the ends of said scanline meet for 2 or 4 character clocks, causing such an effect.

And the blocks moving roughly in sync (more speed away from the Kefrens, less movement when close to the Kefrens), both moving right and left at the same time. So if it's Kefrens moving to the right by 8 pixels, the displacement moves to the right by 8 as well. And when the movement of the Kefrens slows down (say 4 pixels), the displaced background does too, but almost like an exponential curve faster (so moving Kefrens 8 character clocks, displacement also moves 8 character clocks. Moving Kefrens 4 character clocks, displacement moves 2 character clocks in the same direction instead). So the Kefrens sinus movement and the displacement position seem related in a exponential curve kind of way?

I also notice that on the flying saucer in Area 5150 at the end of the effect the saurcer suddenly snaps to the top of the screen and animation freezes for about 1-2 seconds before the next effect of the demo starts. It probably should do that black area over it somehow (those 2 or 3 black areas widening on top of it as in the Youtube recordings), but that doesn't happen in UniPCemu? Any idea what it's trying to do there that's failing?

Also, the effect on Chaplin and credits of Area 5150 improved a bit, although seems to display lots of black scanline on every 2nd row? That's probably the same issue as with the Kefrens on 8088 MPH, but this time it's not moving the start of the scanline vertically(it's at a fixed spot, not moving other than the effects). Of course it not moving is a good thing (stable output), but the next (each 2nd?) scanline seeming to start too early? Perhaps the 8088 being too fast (not enough cycles in some instructions) is the issue here, causing the perceived horizontal display end to be too soon/late by a fixed amount on every scanline?

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Reply 53 of 122, by superfury

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Thinking about it, the same now also applies to instructions with only an imm (no r/m). Is that correct behaviour as well? (Like opcodes, 04/05, 14h,15h (until 3Ch/3Dh), as well as A0-A3 (mov moffs(the immediate),al/ax and reversed direction) and B0-BF(mov reg,imm))

Edit: Leaving the 286+ CPU issue for a bit, I noticed some error on the 808x cycle-accurate timings: the ModR/M EA cycles were calculated, but never applied!

Luckily the main function is more simple now, so implementing it is easy now.
Just implemented the EA cycles to be applied after the final fetching cycle now.

Last edited by superfury on 2023-07-30, 13:13. Edited 1 time in total.

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Reply 54 of 122, by superfury

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8088 MPH now report 1662 (1%) now! 😁
Btw, I'm testing with the Final 8088 MPH version.

Edit: The 16-color noise moved again, to 1 clock before the clock before the "1" starts, as well as the clock before the clock where the 2 of "256 COLORS" starts rendering (as well as the 1st scanline, which didn't change).

Filename
1748-16colornoisemovedagain.png
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6.2 KiB
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File comment
16/256 color noise moved again.
File license
Fair use/fair dealing exception

The Kefrens effect is more close now, with the scanlines (overscan color?) moving left slowly now?
https://www.dropbox.com/s/hwpcquxtmelozda/Uni … 4-41-26.7z?dl=0

Edit: Latest 8088tst3 results:

disk:	real:	comp-d:	disp1:	comp1:	disp2:	comp2:	disp3:	comp3:	disp4:	comp4:	disp5:	comp5:	disp6:	comp6:	disk7:	comp7:
FF36 FF43 <(-13) FF36 <(-13) FF36 <(-13) FF46 >(+3) FF48 >(+5) FF47 >(+4) FF44 >(+1) FF37 <(-12)
FE3C FE59 <(-29) FE3D <(-28) FE3D <(-28) FE61 >(+8) FE65 >(+12) FE66 >(+13) FE60 >(+7) FE43 <(-22)
FDA0 FDC5 <(-37) FDA1 <(-36) FDA3 <(-34) FDD3 >(+14) FDD7 >(+18) FDD7 >(+18) FDD1 >(+12) FDAD >(-24)
FD26 FD58 <(-50) FD27 <(-49) FD28 <(-48) FD63 >(+11) FD67 >(+15) FD67 >(+15) FD5F >(+7) FD3A <(-30)
FCF7 FD2A <(-51) FCF8 <(-50) FCF8 <(-50) FD37 >(+13) FD3C >(+18) FD3D >(+19) FD33 >(+9) FD0D <(-29)
FC31 FC6B <(-58) FC31 <(-58) FC31 <(-58) FC81 >(+22) FC87 >(+28) FC88 >(+29) FC7D >(+18) FC53 <(-24)
FB6D FBB7 <(-74) FB6E <(-73) FB6D <(-74) FBCD >(+22) FBD2 >(+27) FBD4 >(+29) FBCB >(+20) FB9D <(-26)
F93C F9A9 <(-109) F93D <(-108) F93D <(-108) F9C9 (+32) F93E >(+32) F9DE >(+53) F9D2 >(+41) F97F <(-42)
CPU test complete. Elapsed timer ticks:
07F1 07CA <(+27) 07F2 <(+28) 07F1 <(+27) 074D <(-125) 0735 <(-149) 0733 <(-151) 0745 <(-133) 079F <(-43)

Edit: Hmmm... Fixing prefixes to take less time increases 8088 MPH to 1721(3%) cycles? It used to take 3 cycles (including the fetching of the prefix from the PIQ, which took 1 cycle), now being reduced to 2 cycles.

Another issue that was present is that it was counting prefetch cycles as parallel to T1 cycles, which obviously isn't needed?

Edit: Latest 8088tst3 results:

disk:	real:	comp-d:	disp1:	comp1:	disp2:	comp2:	disp3:	comp3:	disp4:	comp4:	disp5:	comp5:	disp6:	comp6:	disp7:	comp7:	disp8:	comp8:
FF36 FF43 <(-13) FF36 <(-13) FF36 <(-13) FF46 >(+3) FF48 >(+5) FF47 >(+4) FF44 >(+1) FF37 <(-12) FF2A <(-25)
FE3C FE59 <(-29) FE3D <(-28) FE3D <(-28) FE61 >(+8) FE65 >(+12) FE66 >(+13) FE60 >(+7) FE43 <(-22) FE26 <(-51)
FDA0 FDC5 <(-37) FDA1 <(-36) FDA3 <(-34) FDD3 >(+14) FDD7 >(+18) FDD7 >(+18) FDD1 >(+12) FDAD >(-24) FD84 <(-65)
FD26 FD58 <(-50) FD27 <(-49) FD28 <(-48) FD63 >(+11) FD67 >(+15) FD67 >(+15) FD5F >(+7) FD3A <(-30) FD0E <(-44)
FCF7 FD2A <(-51) FCF8 <(-50) FCF8 <(-50) FD37 >(+13) FD3C >(+18) FD3D >(+19) FD33 >(+9) FD0D <(-29) FCDF <(-75)
FC31 FC6B <(-58) FC31 <(-58) FC31 <(-58) FC81 >(+22) FC87 >(+28) FC88 >(+29) FC7D >(+18) FC53 <(-24) FC1C <(-79)
FB6D FBB7 <(-74) FB6E <(-73) FB6D <(-74) FBCD >(+22) FBD2 >(+27) FBD4 >(+29) FBCB >(+20) FB9D <(-26) FB65 <(-82)
F93C F9A9 <(-109) F93D <(-108) F93D <(-108) F9C9 (+32) F93E >(+32) F9DE >(+53) F9D2 >(+41) F97F <(-42) F930 <(-121)
CPU test complete. Elapsed timer ticks:
07F1 07CA <(+27) 07F2 <(+28) 07F1 <(+27) 074D <(-125) 0735 <(-149) 0733 <(-151) 0745 <(-133) 079F <(-43) 07F8 >(+46)

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Reply 55 of 122, by superfury

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Why would prefixes taking less EU and BIU cycles for prefixes (proper 2 (1 EU PIQ and 1 prefix parsing) instead of 3(1 EU PIQ and 1 prefix parsing)) return a higher metric cycle in 8088 MPH? Shouldn't it run those instructions faster (less cycles), lowering it instead?

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Reply 56 of 122, by superfury

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GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)).

The motherboard might have waitstates for bus(I/O, 1 on PC and XT afaik) or memory(only on AT). Are these asserted at DMA transfers? I'd assume on S3 state it waits for deassertion? Essentially the same as T3 on the BIU of the CPU?

Edit: Observing default settings, I now see the DMA controller perform 1WS RAM accesses on an XT. Is that correct behaviour (as well as 8088 MPH giving an even higher cycle count: 1744 cycles now)?

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Reply 57 of 122, by GloriousCow

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superfury wrote on 2023-07-30, 21:53:

Why would prefixes taking less EU and BIU cycles for prefixes (proper 2 (1 EU PIQ and 1 prefix parsing) instead of 3(1 EU PIQ and 1 prefix parsing)) return a higher metric cycle in 8088 MPH? Shouldn't it run those instructions faster (less cycles), lowering it instead?

Can't say for sure, but a single cycle can have a big effect - DMA can really be a weird beast. Just having DMA fire off a cycle earlier or later can make a 2-3% swing in execution time.

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 58 of 122, by GloriousCow

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superfury wrote on 2023-07-31, 09:31:

GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)).

No, the difference between PC and XT with DMA is only in regards to the HALT state; it's extremely minor.

superfury wrote on 2023-07-31, 09:31:

The motherboard might have waitstates for bus(I/O, 1 on PC and XT afaik) or memory(only on AT). Are these asserted at DMA transfers? I'd assume on S3 state it waits for deassertion? Essentially the same as T3 on the BIU of the CPU?

Yes, the DMA controller will insert wait states, it has its own ready line and the logic is similar to the CPU READY line. I don't implement that in my emulator; it wouldn't happen on PC unless you did DMA into video memory.

superfury wrote on 2023-07-31, 09:31:

Edit: Observing default settings, I now see the DMA controller perform 1WS RAM accesses on an XT. Is that correct behaviour (as well as 8088 MPH giving an even higher cycle count: 1744 cycles now)?

There shouldn't be any DMA wait states into system memory on PC/XT.

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 59 of 122, by superfury

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GloriousCow wrote on 2023-07-31, 16:20:
No, the difference between PC and XT with DMA is only in regards to the HALT state; it's extremely minor. […]
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superfury wrote on 2023-07-31, 09:31:

GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)).

No, the difference between PC and XT with DMA is only in regards to the HALT state; it's extremely minor.

superfury wrote on 2023-07-31, 09:31:

The motherboard might have waitstates for bus(I/O, 1 on PC and XT afaik) or memory(only on AT). Are these asserted at DMA transfers? I'd assume on S3 state it waits for deassertion? Essentially the same as T3 on the BIU of the CPU?

Yes, the DMA controller will insert wait states, it has its own ready line and the logic is similar to the CPU READY line. I don't implement that in my emulator; it wouldn't happen on PC unless you did DMA into video memory.

superfury wrote on 2023-07-31, 09:31:

Edit: Observing default settings, I now see the DMA controller perform 1WS RAM accesses on an XT. Is that correct behaviour (as well as 8088 MPH giving an even higher cycle count: 1744 cycles now)?

There shouldn't be any DMA wait states into system memory on PC/XT.

The issue in this case is that the DMA controller is programmed into memory read mode. So that means: read from memory, write to I/O in my emulator.
The I/O device isn't registered for the RAM Refresh, but the DMA controller will still perform a port OUT to it (although it discards the actual access because no write handler is registered).
And that very same I/O device write is the one triggering the 1WS (because the motherboard logic thinks it's trying to write to I/O, which has a defined 1WS, just like the CPU).

Edit: Just modified the DMA triggering of motherboard waitstates to only trigger what responds. So if a read/write handler exists(for I/O) it uses the bus waitstates (the same with a write handler) as well as memory waitstates. If none exists, it's just memory waitstates.
In verify mode, it's just bus waitstates, but no memory waitstates (as nothing is written to memory).

If the I/O device triggers waitstates in it's read handler, that's applied after the motherboard I/O waitstates (and memory waitstates) now.

Now the 8088 MPH metric cycle count is back to 1721 cycles (3%).

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