When you've done enough research on the 8088, some of the things that Intel documentation has to say about it starts to sound a bit... suspect.

From the "iAPX 86 88 186 188 User's Manual" section 1-24:

If the EU needs access to memory, it may have to wait for up to one clock if the BIU has already started an instruction fetch bus cycle.
(The EU can detect the need for a memory operand and post a bus request far enough in advance of its need for this operand to avoid waiting a full 4-clock bus cycle).

As far as I can tell, this is nonsense. The EU issues a bus request when it executes a particular line of microcode that requests a bus operation (read or write). There's nothing I can see in the microcode that would flag a bus request in advance, or provides advance notice of a bus request in any way.

In the scenario where the EU requests a bus operation on T3 of an active code fetch, it will have to wait not "up to one clock" but 4 clocks - T3 and T4 of the code fetch, then two TI states in which a prefetch abort is performed. "Up to one clock" my big bovine derrière.