I'm posting this here as I don't plan to update my blog thread going forward - it's a bit spammy, and after all if you want to follow updates to my blog, an RSS feed is available.

But I believe this particular post is of significant interest to mention separately:

https://martypc.blogspot.com/2023/08/the-8088 … -algorithm.html

I believe I have come up with a simple model that fully describes the 8088 prefetch algorithm and its miscellaneous related bus delays. By implementing EU bus operation timing based on the microcode and combining that with this BIU logic, a cycle-accurate 8088 CPU implementation should now be fairly straightforward to accomplish.