I've been testing somewhat on the i440fx emulation of the PCI IDE controller.

Now, I've found something interesting.

The documentation says the following about the bit 15 of register 40h/42h (82371FB (PIIX) AND 82371SB (PIIX3)
PCI ISA IDE XCELERATOR):

2.3.10. IDETIM—IDE TIMING REGISTER (Function 1) Address Offset: Primary Channel=40–41h; Secondary Channel=42–43h Default Value: […]
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2.3.10. IDETIM—IDE TIMING REGISTER (Function 1)
Address Offset: Primary Channel=40–41h; Secondary Channel=42–43h
Default Value: 0000h
Attribute: Read / Write Only
This register controls the PIIX's IDE interface and selects the timing characteristics of the PCI Local Bus IDE
cycle. Note that primary and secondary denotations distiguish between the cables and the 0/1 denotations
distiguish between master (0) and slave (1).

And

Bit Description 15 IDE Decode Enable (IDE). 1=Enable; 0=Disable. When enabled, I/O transactions on PCI targeting the IDE ATA reg […]
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Bit Description
15 IDE Decode Enable (IDE). 1=Enable; 0=Disable. When enabled, I/O transactions on PCI
targeting the IDE ATA register blocks (command block and control block) are positively
decoded on PCI and driven on the IDE interface. When disabled, these accesses are
subtractively decoded to ISA.

So that basically says: if bit 15 is set, it's in PCI mode(positively
decoded on PCI), otherwise it's in legacy mode (subtractively decoded to ISA).

I kept struggling with the detection/booting process of the PCI IDE controller in legacy vs PCI mode. I did everything the PIIX/PIIX3 documentation said: When register 40h/42h bit 15 was set, set the controller in PCI mode (using the registers in the BAR0-3 that are setup). If it wasn't set, used legacy I/O addresses instead (1f0/3f4 and 170/374).

The thing is, whenever it was setting those bits (masked by the register 04h bit 0 being set, thus enabling the IDE devices connection to the CPU), it would always power up the device in PCI mode instead, never detecting the drives or posting properly.

So it looks like the PCI mode is actually the inverse of that? So clearing those bits sets it into PCI mode, while setting those bits puts the channel in legacy mode (compatible with older motherboards, at legacy IRQ and I/O addresses whatever the values in the registers are). So the documentation seems to swap the PCI and legacy(ISA) terms?

Then there's another little caveat (which is undocumented it seems, noticed behaviour on the i430fx motherboard): when the second channel is then put in PCI mode but the first channel is in legacy mode, the second channel uses the BARs from the primary controller instead of the expected secondary controller!
Also, the PIIX seems to have all those bits as is documented (1 being PCI mode, 0 being ISA(legacy) mode), unlike the PIIX3!

Edit: Hmmm... Now with the latest changes, the i430fx BIOS doesn't ever seem to set the bit 15 of the 40h/42h registers, no matter what the setting used in the BIOS CMOS configuration utility is? Although that keeps it in legacy IDE mode, it doesn't match the i440fx behaviour?