I plan on modifying my AMI Mark V Baby Screamer (VLSI 330/331/332) and Chainech 340 (SiS 310/320/330) motherboards to properly […]
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I plan on modifying my AMI Mark V Baby Screamer (VLSI 330/331/332) and Chainech 340 (SiS 310/320/330) motherboards to properly support the L1 cache of the Cyrix 486DLC and 486SXL processors using the FLUSH# pin. The hardware mod is quite simple and can be accomplished with a single NAND quad or dual channel package (74F00N).
The problem I am having is that I cannot determine if the L2 cache on these motherboards uses look-aside (parallel) or look-through (serial) scheme. Reading the chipset data sheets did not provide a direct answer. With parallel access, both, the cache and the main memory are accessed simultaneously. If a cache hit occurs, the access to the main memory is aborted. In serial access, the cache is first examined and, if a miss occurs, the main store is accessed.
Instructions from the Ti486DLC Reference Guide are shown below. For parallel L2 cache, we are instructed to take the HLDA pin from the CPU's HLDA pin. This is straight forward enough. However, if I were to make an educated guess, I would say these motherboards likely use serial L2 cache access. How can I be certain?
However, for serial L2 cache, we are instructed to take the HLDA pin from the motherboard's chipset. Looking at the SiS board's chipset, the HLDA pin's input is directly connected to the CPU's HLDA output. So I cannot figure out how to differentiate between the two Ti connection schemes on this motherboard. Perhaps I am supposed to use DMAHLDA from the chipset instead?
Alternately, the VLSI motherboard has a chipset pin HLDA as an input in, which is not direclty connected to the CPU's HLDA pin. I am confused as to why it is an input and not an output pin.
[click to enlarge]Parallel_L2.png[click to enlarge]Serial_L2.png