First post, by Battler
Does anyone here any idea on how this actually works?
Based on the documentation, I get this:
Sequencer register 04h, bit 2:
O/E Dis. -- Odd/Even Host Memory Write Adressing Disable
"When this bit is set to 0, even system addresses access maps 0 and 2, while odd system addresses access maps 1 and 3. When this bit is set to 1, system addresses sequentially access data within a bit map, and the maps are accessed according to the value in the Map Mask register (index 0x02)."
Graphics register 05h, bit 4:
Host O/E -- Host Odd/Even Memory Read Addressing Enable
"When set to 1, this bit selects the odd/even addressing mode used by the IBM Color/Graphics Monitor Adapter. Normally, the value here follows the value of Memory Mode register bit 2 in the sequencer."
Graphics register 06h, bit 1:
Chain O/E -- Chain Odd/Even Enable
"When set to 1, this bit directs the system address bit, A0, to be replaced by a higher-order bit. The odd map is then selected when A0 is 1, and the even map when A0 is 0."
Miscellaneous output register, bit 5:
O/E Page -- Odd/Even Page Select "Selects the upper/lower 64K page of memory when the system is in an eve/odd mode (modes 0,1,2, […]
O/E Page -- Odd/Even Page Select
"Selects the upper/lower 64K page of memory when the system is in an eve/odd mode (modes 0,1,2,3,7).
= 0 selects the low page
= 1 selects the high page"
But how does this actually work? I suppose it is like this:
- Sequencer register 04h, bit 2, when set to 0, enables Chain-2 / Odd/Even mode on writes from CPU to VRAM;
- Graphics register 05h, bit 4, when set to 1, enables Chain-2 / Odd/Even on reads from CPU to VRAM;
- Graphics register 06h, bit 1, when set to 1, enables Chain-2 / Odd/Even on reads from VRAM to DAC;
- Miscellaneous output register, bit 5 controls whether the high or low page is used - as in, 0/2 when clear, and 1/3 when set.
Am I interpreting this right?