vladstamate wrote:I think it is more complicated than that. Here is an excerpt from Michael Abrash's book: http://www.phatcode.net/res/224/files/h […]
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I think it is more complicated than that. Here is an excerpt from Michael Abrash's book: http://www.phatcode.net/res/224/files/html/ch11/11-02.html
Few things to slow down the theoretical 3 cycles per 32bit transfer that a 386DX should be able to do:
- My guess is 1WS memory was not that common but 2-3 was.
- the DRAM refresh seems to steal cycles. I do not know how much and when exactly.
- my other guess (based on Abrash) is that the number of WS varies with this: "which interleaved bank and/or RAM column was accessed last."
I think some more knowledge of the DRAM architecture is required to fully understand this...
It all gets very messy, particularly as CPU clock speeds increased!
I've just dug out the PS/2 model 70 reference manual - this is a 386DX system with 16, 20 and 25 MHz versions, with varying memory systems across the three. The 16 MHz version is using fast page mode RAM with no cache, with the below performance :
- Memory Read (Page Hit) - 0 wait states
- Memory Read (Page Miss) - 2 wait states
- Memory Write (Page Hit) - 1 wait state
- Memory Write (Page Miss) - 2 wait states
They don't state what a page is, on a 1 MB system with a 32-bit data bus this will probably be implemented as 256kx32, meaning 18 address bits. This would make a page 9 bits + 2 to account for the 32-bit bus, giving a page size of 2 KB.
The 20 MHz version uses the same timings, but presumably needs faster DRAM to achieve them.
The 25 MHz version adds a 64kb cache, with the below timings :
- Memory Read (Cache Hit) - 0 wait states
- Memory Write (Cache Hit) - 0 wait states
- Memory Read (Cache Miss, Page Hit) - 0-2 wait states
- Memory Write (Cache Miss, Page Hit) - 1 wait state
- Memory Read (Cache Miss, Page Miss) - 3-5 wait state
- Memory Write (Cache Miss, Page Miss) - 0 wait states
The manual states that writes are buffered on the motherboard, hence the odd write timings. I suspect my 386DX/40 board is doing something similar. It doesn't say what the variations in the read timings are caused by, which is extremely helpful from an emulation perspective.
Refresh for all three is given as performed every 15.1us, with delays from 500 to 600 ns - this would work out as roughly 5-7 cycles.