Interesting. I'll have to check mine out when I get it.

Ok, everybody needs to check out this setup: Performance comparison of CPU: 286-25 vs 386DX-25 vs 386SX-25

Moogle! wrote:

For 20Mhz, you would need 50ns, which is rare as hens teeth and no one buying a 286 at that point was going to be buying something as expensive as 50ns ram.

So you say I shouldn't even care that my 286-20 works in 1WS mode and I don't know how to change this?
This way it's about as fast as a 16MHz 0WS one.
But I remember a board that could work in 0WS mode at 20MHz (but that one had issues with starting up, with GUS, and slow ISA video access). And I don't even have any 50ns RAM 😕

20 MHz works fine with 60ns RAM, because the CPU doesn't access RAM in every cycle and also you can access RAM always slightly faster than it is specified for. It may not be fully stable or the RAM may run hot, however, which is why you may add heatsinks to the RAM chips.

I believe EKB's 286 ran 0 wait state with dram 20 pin chips and a simple aluminum cooler epoxied on top of them.

I wonder if that is why my model has a 40Mhz crystal on it, instead of a 50Mhz one.

Apolloboy and I actually picked up one of those PCChips M205 boards from Weirdstuff Warehouse back around 2012, but didn't realize it was PCChips at the time. Came with 1MB of 80 ns DRAM probably with 1 wait state enabled and was a bit slower than expected when we got it up and running. (also we only got DOS working with the base 640kB, but I don't think we had expanded memory drivers installed, or not the right ones)
A week or two after that we also found 3 more 286-20 boards there, but didn't pick any of them up. I forget exactly what they were, but I think one had a Hedland chiset, the other two looked like similar PCChips 200 series boards and all 3 had SIPP or SIMM sockets on them rather than the DIPP ones ours had. (so probably M209 or 216, since I don't recall a soldered-on CPU like the 219, plus the 219s usually seem to come with 25 MHz CPUs, which would've been more memorable) OTOH there's actually a lot of relatively cheap 60 ns 256kx4-bit DIP RAM on ebay right now, so upgrading that 205 is actually cheaper/easier than finding 60 ns RAM for a SIMM based system.

On the topic of DRAM timing, it should be noted that it's dependent on both the timing tolerances of the RAM itself and the speed (clock period used for minimum timing granularity) of the memory controller that determines what sort of wait states need to be used. (then there's also other considerations like the chipset's DMA timing, if DMA is supported, and the particular CPU's access time as well as read/write cycle time: the older 8088 and 8086 use the same 2-clock-tick access time constraint as the 286/386, but take another 2 ticks to complete a memory cycle, so slower DRAM cycle times can be used for consecutive reads/writes without wait states, though you also have a longer period where data needs to be valid on the bus, meaning the chipset either needs a data latch for the CPU or long, slow, loose bus cycle timing conforming entirely to the 4 CPU clocks per access: I'm not sure, but the Tandy 1000 may use a bus latch to allow interleaved DMA for video, with 2 memory accesses per 4 CPU clocks like the Amiga and Atari ST use, plus some 8-bit computers)

In any case, the 286-25 here: Performance comparison of CPU: 286-25 vs 386DX-25 vs 386SX-25 may have a faster memory controller than some or all of the PCChips boards use (those PCChips boards also all seem to be from around 1988/1989, or at least the BIOS revisions are, which seems a fair bit older than the 1992-1993 compact baby AT 286-16 boards out there) in which case the memory controller might actually work at 50 MHz (or use 2-phase logic at 25 MHz) which would make 60 ns DRAM fit perfectly with zero wait state CPU access. (however, typical 60 ns FPM DRAM can't cycle at 80 ns, so there would need to be waits inserted to fast, consecutive CPU accesses like for really fast/short instructions or prefetch filling; with a fast controller you might get away with 120 ns cycle times with 60 ns RAM, which would be 3 CPU clocks, but 160 ns would be more realistic)

https://www.matrix-bios.nl/calc/waitstates.html
take that calculator, plug in 25 MHz for the CPU and 20 ns for the delay (50 MHz memory controller, 20 ns timing delay)

Now for a slower, 25 MHz memory controller (25 MHz single-phase clock, 12.5 MHz 2-phase) you'd have 40 ns memory controller cycle periods, meaning 40 ns DRAM, which wouldn't be doable (at least with DRAM of that vintage: you will see some FPM and especially EDO DRAM or VRAM at that speed and faster in mid/late 90s graphics cards and some embedded systems: I have a Rage II+ with 35 ns EDO or BEDO chips onboard for example; SDRAM with access timing in that range was used a lot more often, though).
So realistically, with that slower memory controller in a 25 MHz system, you get 1-wait state access times and 80 ns memory (which was pretty well in the mainstream speed range around the time these boards were new in 1988-1992), so from that standpoint it'd be a really well-matched combination for the time (same for 386SX and SX-25 systems) while 286-20 systems using similar slower DRAM controllers (50 ns cycles) could get away with 100 ns DRAM for 1-wait state, but would need 50 ns for zero wait state (impractical). Though a fast 40 MHz memory controller would allow zero wait states with 80 ns DRAM on the 20 MHz 286. (90 ns for a 16.67 MHz 286, 120 ns with a 12.5 MHz 286, also 94 ns for 16.0, which is probably close enough for nearly all 100 ns DRAM, plus 75 ns for a 20 MHz system, so 70 ns chips or probably 80 ns in a good number of situations)

There may also be cases where the memory controller clock is 1.5x that of the CPU (or 3-phase at 1/2 the clock speed, or using assymetric 2-phase timing pulses) where you could have cases like a 10.67 MHz CPU clock and 62.5 ns memory controller timing. (thus allowing zero wait states with 125 ns DRAM, which seems to go right along with a number of 286-10 and turbo XT systems)

OTOH, that also means that, for memory access/bandwidth bound operations and software, a zero wait state 286 at 12.5 MHz would be just as fast as that 286-25 and faster than the 286-20, but that wouldn't hold true for operations/applications with any significant use of slower, complex instructions with many cycles spent between bus accesses (multiplication and division for example) and instructions making heavy use of register-register operations.

Also chipsets that supported page-mode read/write operations would partially or entirely avoid the need for wait states for consecutive reads/writes. (this includes the page-mode function of most older, NMOS DRAM chips as well as CMOS Fast Page Mode chips; for NMOS chips the mage-mode cycle time is usually the same as the RAS access time: ie a 120 ns rated chip would do 120 ns page-mode cycles; FPM DRAMs could do a good bit better than that provided the memory controller was fast enough to set-up the right parameters, otherwise they should be perfectly compatible with NMOS page mode timing)

Also, at the clock speeds in question here, I don't think increased heat generation would be a significant factor on the DRAM chips themselves. For that matter NMOS DRAMs (like NMOS logic) shouldn't have any power dissipation change at higher or lower clock rates, while CMOS DRAMs would be lower power across the board but would consume more power when cycled more rapidly. (and I think CMOS chips would comprise all 60 ns chips out there and a lot of the higher-density slower chips, but there certainly were 70 ns NMOS DRAMs: in fact NEC made 70 ns 64kx4-bit DRAMs with 140 ns cycle time ratings and got used for the zero wait state work RAM of the PC Engine CD-ROM2 of 1988 to mesh with the 7.16 MHz 65C02 derivative in it: 70 ns access 140 ns cycle time constraints)
Most of the DRAMs actually used back around 1990 would've still been NMOS chips, especially the 32kB (256kbit) chips, though I think there were 128kB (1Mbit) NMOS chips too. (most seem to be CMOS though, I'll check the datasheet on my 205's 80 ns chips at some point ... and to see if both the 256kx4-bit and 256kx1-bit DRAMs are the same type)

That said, chips can generally have more room for exceeding rated specs when kept cooler and one reason many chips will operate well beyond their official ratings is due to the maximum temperature rating included in those specifications. (you'd only get close to the maximum thermal ratings of most chips in extreme environments, like some industrial, military, or special hot climate applications, or in very cramped, poorly ventilated enclosures next to other hot components: like a cramped, very compact, all-in-one computer with integrated monitor and only passive cooling)
That issue came up during the design of the Atari ST with its use of 250 ns (249.67 ns in the original 520ST) DRAM cycle times using chips nominally rated for 260 ns minimum (not to mention running some individual timing parameters particularly tight when you look at the whole break down; there's a couple threads on Atariforum that dig into investigating that and pulling up quotes from Atari Corp engineers on the topic)
The ST's DRAM controller runs of a 16 (16.0212) MHz clock, but appears to have half-cycle granularity (effectively working at 32 MHz and able to set DRAM timing pulse widths on a 31.2 ns basis). I'm not sure if the Amiga does the same thing or if it just abuses timing a bit more and uses a straight 14.32 MHz memory controller clock (or half-cycle 7.16 MHz) with similar 150 ns DRAM chips. (doing 279.4 ns memory cycle times, which is well within the 260 ns minimum, but having 69.84 ns granularity of pulse width would force other parameters further out of spec than what Atari was doing, like cutting RAS to 139.7 ns)

Or in other words, the Atari ST's memory controller was working fast enough to allow that same 150 ns DRAM to work with zero wait states in a 10.7 MHz 286 system. (or 8086, or 68000; in the ST, with CPU memory cycles hardwired to the 250 ns slots, so even if access timing is fast enough for a faster clocked CPU, you get wait states for any instance where the CPU does an access more than once in that 250 ns interval or when you have instructions that take a non-multiple-of-4 cycles to execute, though that should've meant 10 MHz 68000s would have worked nicely with a mix of 0 and 1 wait state accesses or 12 MHz with a mix of 1 and 2 waits, and I seem to remember some 12 MHz and 16 overclock mods/hacks that took advantage of this, but performance gain in typical software was minimal due to unchanged memory bandwidth ... but multiplication and division operations were almost 2x as fast at 16 MHz)

Bear in mind DRAMs always have an analog component to them in as far as capacitive charge for each memory bit, need for refresh and precharge sufficient to avoid errors/data loss. (if charge is too low, a DRAM read would be destructive, and likewise insufficient refresh would allow data to degrade due to capacitance leakage)

Oh for that matter, I wonder how much wait states help stability of the 8-bit expansion bus on turbo XT systems above 10 MHz. (since 8088s have the 4-clock memory cycle limitation, 1 wait state in 12 MHz systems should make the bus effectively operate at 8 MHz, and 2 waits at 16.0 MHz should do effective 10.67 MHz 93.75 bus cycle intervals: which would be in line with most 10 MHz turbo systems)

Managed to get this motherboard running with Harris 25Mhz and 60ns memory modules , it would not work with 70ns , but it only works with 2 x 1mb modules when i use 4 x1mb modules it freezes . Is there a manual for this ? What could be the problem ?

moumiaq wrote on 2021-06-11, 06:28:

Managed to get this motherboard running with Harris 25Mhz and 60ns memory modules , it would not work with 70ns , but it only works with 2 x 1mb modules when i use 4 x1mb modules it freezes . Is there a manual for this ? What could be the problem ?

I've had similar issues with other 25MHz 286 systems when trying to run at 0 wait states. Also at that speed the RAM got hot.

I only managed to get two of my four 60ns modules to run at those settings. At 20MHz everything is fine, in fact I can get a couple more MHz out of those systems until 60ns RAM becomes marginal.

If you go back through the more technical posts before, the short story is that because the 286 access RAM at clock speeds you need 50ns (or better) modules at 25MHz and 0ws. I don't think such modules exists which is why those of us building hotrod 286 systems have very much hit and miss results.

It's proven that it's a waste of time to run 25MHz and 1ws - it's no faster (slower in most cases) than 16MHz 0ws setup.

megatron-uk wrote on 2021-06-11, 07:19:

If you go back through the more technical posts before, the short story is that because the 286 access RAM at clock speeds you need 50ns (or better) modules at 25MHz and 0ws. I don't think such modules exists which is why those of us building hotrod 286 systems have very much hit and miss results.

It's proven that it's a waste of time to run 25MHz and 1ws - it's no faster (slower in most cases) than 16MHz 0ws setup.

So although some of these 286 motherboards support up to 16mb of ram we are stuck with 2mb of ram with the fastest cpu for 286 ? What were they thinking back then ?( rhetorical question 😀 )

No, it's just that there are no 30pin modules that were produced at an officially rated 50ns (or faster) speed. You might have better luck with some other 30pin modules, but you'll not know until you hand pick them and/or use a memory tester to pick out the absolute cream of the crop.

From what I've found over the last few years, I don't believe that any of the 25MHz 286 systems that were sold at the time would have been 0ws enabled. Remember that the 25MHz part was very late in the life of the 286, and I suspect that any that were sold were installed/configured to run at 1ws or used BIOSes that automatically configured memory for 1ws with no option to change it.

Actually, there are very few 286 support chipsets that are rated to run at 25MHz anyway. Most seem to be based on either the VLSI VL82C200, or a later 386SX chipset (a lot of which are dual 286/386SX compatible). It explains why there are so few true 25MHz 286 systems around (the fact that a 25MHz 0ws 286 absolutely trashes a 386SX of the same speed probably didn't help at the time!).

That m216 board runs easily at 25mhz with 16mb ram.
It takes pretty much any 60ns RAM modules I throw at it.
In fact it can go up to 32mhz without any effort, but I suppose it has internally established wait states.
Unfortunately it's interactive graphics performance is one of the worst I have seen to date.

megatron-uk wrote on 2021-06-11, 07:19:

It's proven that it's a waste of time to run 25MHz and 1ws - it's no faster (slower in most cases) than 16MHz 0ws setup.

you mean 20MHz 0WS - it is definitely faster than 16MHz 0WS

Apologies, yes I was conflating the general case of 20MHz 1ws and 25MHz 1ws performance.

Most of the benchmark tests I've ran show a 25MHz 1ws configuration is equivalent to somewhere just over 16MHz 0ws, but well below 20MHz 0ws.

However, real-world application testing in Wolfenstein 3D showed that 25MHz 1ws configuration actually brought down the whole system performance to worse than 16MHz 0ws (returning 11.4fps vs 11.6fps on the same hardware).

I'm wondering if Wolf3d is such a good benchmark, I didn't question it when I had a version 1.2 or something kicking around, that was too fast a third of the way up the 486 performance tree... faster machine, faster wolf, checks out... then I put version 1.4 on a PII, expecting it to be really silly... nope, it is playable.. not hair touch of a key and fly across the room like 1.2(?) would on anything faster than about 20Mhz. ... it has a timing test loop or something in it to slow it down.

BitWrangler wrote on 2021-06-11, 14:38:

I'm wondering if Wolf3d is such a good benchmark, I didn't question it when I had a version 1.2 or something kicking around, that was too fast a third of the way up the 486 performance tree... faster machine, faster wolf, checks out... then I put version 1.4 on a PII, expecting it to be really silly... nope, it is playable.. not hair touch of a key and fly across the room like 1.2(?) would on anything faster than about 20Mhz. ... it has a timing test loop or something in it to slow it down.

I don't know where it starts to tail off, but certainly on 286, 386 and low-end 486 (a DLC40 in my case) it scales quite nicely and is a nice demonstration of the difference that enabling/disabling cache, swapping video cards, changing memory timings etc seem to make to an otherwise identical system.

megatron-uk wrote on 2021-06-11, 07:57:

No, it's just that there are no 30pin modules that were produced at an officially rated 50ns (or faster) speed.

Above statement is false

I can clearly show you many period advertisements advertising 0 wait states
45-56ns system memory in their mid-range to upper range offerings with all sorts of cpus.

What I always found strange is how
0 Wait States
And 56.5NS

Would be prominently shown in every advertisement until sometime in 1991 around the advent of 50ns memory and then all of a sudden nobody mentioned 0WS or memory speeds except in tiny letters.

It’s like everyone forgot the previous 12 years of advertising memory speeds and 0 wait states as a big deal which now totally didn’t matter anymore.

The strange oddball NS claims all disappeared and while 50ns was a big deal prominently advertised through 1991 nobody mentioned anything that fast in 92.

Always found it strange that all you needed after 1991 was slow 60,70 or 80ns memory and faster memory though listed in the computer shopper was some kind of expensive back alley alchemy

rmay635703 wrote on 2021-06-12, 02:07:

Above statement is false […]
Show full quote

megatron-uk wrote on 2021-06-11, 07:57:

No, it's just that there are no 30pin modules that were produced at an officially rated 50ns (or faster) speed.

Above statement is false

I can clearly show you many period advertisements advertising 0 wait states
45-56ns system memory in their mid-range to upper range offerings with all sorts of cpus.

What I always found strange is how
0 Wait States
And 56.5NS

Would be prominently shown in every advertisement until sometime in 1991 around the advent of 50ns memory and then all of a sudden nobody mentioned 0WS or memory speeds except in tiny letters.

It’s like everyone forgot the previous 12 years of advertising memory speeds and 0 wait states as a big deal which now totally didn’t matter anymore.

The strange oddball NS claims all disappeared and while 50ns was a big deal prominently advertised through 1991 nobody mentioned anything that fast in 92.

Always found it strange that all you needed after 1991 was slow 60,70 or 80ns memory and faster memory though listed in the computer shopper was some kind of expensive back alley alchemy

My guess would be that 486 CPUs with L1 cache and L2 cache on motherboards becoming available at affordable prices reduced the significance of RAM performance, to a point . Prior to that, cache memory was, AFAICR, an expensive proposition and required a dedicated cache controller such as the Intel 82385 . Cache-less systems would more directly benefit from faster RAM, whereas systems with cache(s) were more isolated from main memory performance .

I am going from memory (no pun intended), so please feel free to correct me .

EDIT: In other words, marketing likely shifted from being RAM speed centric to cache centric.

rmay635703 wrote on 2021-06-12, 02:07:

I can clearly show you many period advertisements advertising 0 wait states
45-56ns system memory in their mid-range to upper range offerings with all sorts of cpus.

Can you, please? Because I certainly have seen them for up to 20MHz processor clocks, but not beyond