Only the last 13 bits should matter. You make a shift reg that is 13bits wide and keep loading it while tossing out the bits loaded earlier and when latch signal goes low you use the 13bits that remain in the shift reg. If the chip sends 18 bits then first 5 should be garbage and not be used.

It was my first guess, but seems there is something more to this... Will try a few things...

Until I built a highly complicated 😀 test bench:

I couldn't figure out how is that think working... Still not sure, if I can't read properly, or the datasheet is wrong about exponent calculation... Basically, I was shifting the mantissa in wrong direction...

Now the sound at least recognizable - https://clyp.it/spfvlvlc

Found another bug in my code (one number was in a binary form instead of hex)… I think it's quite impressive for just an one resistor/capacitor DAC - https://clyp.it/evbuxhem 😀

Yea, this sounds very good!

Small improvement - better signal-to-noise ratio - https://clyp.it/kemugmbb

why not implent opl2 too ?

matze79 wrote:

why not implent opl2 too ?

Are you talking about implementing OPL2 inside of FPGA ?

Probably, final version of DAC part (sigma-delta instead of simple PWM, more bits etc) is here, the output - https://clyp.it/0f4ujcv5

newold86 wrote:

Small improvement - better signal-to-noise ratio - https://clyp.it/kemugmbb

Pretty amazing but I would have thought there would be so much less noise with something as clean as an FPGA? I would most certainly be interested in a programmable OPL3 card like this that could emulate other cards..

I believe quite a bit of this noise is produced by OPL2 itself. Also don't forget FPGA is producing purely digital signal, and I use the world's simplest DAC (ONE resistor and ONE capacitor - that's all) to convert that digital one-bit signal to analog sound. FPGA's GPIOs are not made to provide precise clean voltage required for high quality sound - margins for 0 or 1 are really wide, so for me it's amazing that FPGA's digital GPIO good enough for 12-bit DAC...
By the way, the latest version of DAC implementation is even better - https://clyp.it/kemugmbb ...

If one uses an external single logic gate powered with a very high PSRR power regulator you can get fairly clean output. But costwise it makes little sense as you can get a decent DAC for that money already.
The last recording is probably as close as it will get to the best possible output on the FPGA with the method used.

It is indeed pretty decent.. I have no PCs that need an 8 bit sound card but if I did I would be ok with using this for OPL2. Any chance of it doing SB conpatible digital audio in the future? Or is the project scope limited to only an Adlib card clone?

appiah4 wrote:

It is indeed pretty decent.. I have no PCs that need an 8 bit sound card but if I did I would be ok with using this for OPL2. Any chance of it doing SB conpatible digital audio in the future? Or is the project scope limited to only an Adlib card clone?

Seems like I wasn't clear enough... Actually, main reason to build this project was to check some things on DSP side. Certainly just an OPL2 part does not require MAX10 FPGA 😀

At the moment it fully (to my best knowledge) supports DSP 2.01, including all undocumented commands I could find.

Example of the digital audio out - https://clyp.it/gafprduq

Right now I'm working on digital audio in (I know, no one needs it, but I'm curious) using FPGA's ADC. Sometimes I can get out very similar what I'm feeding in 😀, but still a lot of space for improvement...

Technically, if I get my hands on cycle-accurate 8051 core, I can try to use a firmware from original SB - again, no practical reason, but one more challenge 😀

Do you plan to commercialize this? Do you need testers etc? I would be ok with paying a reasonable sum for a development board to play around with once you think it's semi-mature 😀 I love playing with modern-retro hardware like this, and the stuff Serge makes.

appiah4 wrote:

Do you plan to commercialize this?

I'm sorry - all my projects are just for fun, no commerce... Usually I loose an interest before they are even "semi-mature", after that either they go on the shelf (most of the time), or I give them away to someone who can do their own research/design. My projects are almost never commercially viable - quite an overkill with parts (way too expensive and often difficult to solder at home - BGA packages etc). I think for modern-retro SB card something like BLASTERBOARD : A new SB 2.0-compatible ISA sound card is more interesting for you (actually, last year I had an idea to design something like that, even acquired the parts, but than changed my mind to something more complex and useless 😀 ).
And I happily give away all my design files to someone who really has a desire/skills to do something with it...

I'm also following that project but to be honest it's not half as interesting as an FPGA sound card to me. I have none of the skills to do this, but I hope you get it to a stage someone else may pick up and go ahead with. (Paging Serge maybe?)

Just curious - what does make you interested in FPGA version ?

newold86 wrote:

Just curious - what does make you interested in FPGA version ?

I like the idea of emulating older hardware in fpgas; it's the same reason why I am so interested in many newer Amiga accelerator cards like the Vampire and things like the Mist, Minimig etc.

An idea if you lose interest in this project: put the design files on github and let other people pick it up. This way your work does not go to waste.

newold86 wrote:

I use the world's simplest DAC (ONE resistor and ONE capacitor - that's all) to convert that digital one-bit signal to analog sound.

That's interesting. Sounds like how the PC speaker circuit is constructed. How exactly do you drive this? You have a high-resolution timer? What frequency does it run at?