4 way associative.

What I mean is(as UniPCemu implements it):
- It uses a set, based on the lower 2-bits of the logical frame(bits 12-13). Currently it's still bits 29-30.
- Said set has 8 TLB entries. Those are dynamically allocated using a simple linked list for speed(allocation and deallocation is done using two linked lists. It simply moves the entry to the top of the allocated or deallocated linked list to (de)allocate it).
- Looking up within a set simply itherates the allocated linked list(for performance) with the MRU being at the top and LRU at the bottom(both top and bottom of the linked list are kept in pointers for easy LRU to MRU(when no deallocated available), random to MRU(from an entry in the allocated list when reading/writing said entry) or unallocated to MRU(top of free list to top of allocated list(automatic MRU)).

That way, there's a fast and efficient LRU algorithm and set-associative TLB lookups/stores?

Is that correct behaviour?

Just reread that section. So the 'set' is essentially a block of four entries(that contain four addresses), selected by the low 3-bits of the tag's address. Within those four entries, it uses one of them to allocate/read/write/use/free a (new) entry.

So it's the same as the 8 entry four ways with a 80386?

I've just confused the way and entry in my TLB implementation?

So:

There are 32 entries in total. 4 entries for each set(set selected by the low 3-bits of the LA address). Then lookups/writes, allocation and deallocation are only on those four entries(ways), determined by the 3-bits of the LA?

So that 'way' are the four entries that are selected by the set(which is the least significant 3-bits of the LA). Then the lookup results in a tag, way(which of the four had a result) and translated address for that way and set combination?

Is that correct?

Edit: So this is the opposite of a 80386, which performs lookups on a set(2-bits) of 8-entries within a set?
https://pdos.csail.mit.edu/6.828/2014/reading … i386/s10_06.htm

So, essentially the 80486 doubled the set size(doubled the set lookup size to select what to hit possibly) and halved the entries that result for said set(4 instead of 😎?

So the 80386 has 4 sets of 8 entries to use, while to 80486 has 8 sets of 4 entries to use?

Looking at the 80386 and i486 programmer's reference manual's description of the TR6&TR7 registers reveals something interesting: they say the same(minus the P-bit for TLB writes).

So it's actually 4 ways(sets incorrectly labeled for 386 instead of ways) with 8 sets for both. Ways are selected by the low 3-bits of the address. Then a set for said way is returned/written.

So, if reading it again, I've understood it correctly:
- A lookup/store has a set, determined by the low 3-bits of LA(bits 12-14).
- The associative entry(four of them) return a result(an entry with an array index(stored in the REP field of the TR6/TR7 on lookups/stored) of a set, which is a list item.
- Said entry is usually automatically allocated, or forced a specific one when P=1(then REP is used to select one of the four ways in the pool, index in UniPCemu). Otherwise, it's automatic(normal paging algorithm(LRU) using two linked lists)?

Just reversed the whole set vs way logic in UniPCemu(only TLB changes with their calls from the Paging emulation). Now it's Set-associative instead of Way-associative(which it was until now, from TR6/7(also in execution, especially noticeable when using TR6&7, since it used the associative memory in an incorrect way)).