First post, by Kidrash
Hello,
i'm trying to understand how a bios parted in 2 chips is used by the CPU.
I'm trying to disassembly a bios to understand some post codes sent to the LPT1 (Olivetti M290S does that) but i'm having troubles wit IDA.
First, let's say i know nothing about disassembly, machine code and such but i'm reading and watching some tutorial to get some ideas.
I load the 2 .bin files into IDA and at FFF0 (reset vector) i don't have the jump intruction EA.
The first EA instruction it's at FFF8, the same address i get with logic analyzer hooked to the Eprom on the motherboard.
With Winhex i can merge the files, first low and then high one and i get something better to read. And now at the bottom i get the "magical" sequence EA 5B E0 00 F0
(jump to f000:e05b) but..... it's at location 1FFFF cause the files have been merged togheter.
So in some ways the chipset translate the FFF0 address from the CPU to FFF8 in the rom and send the data back in the correct order.
In IDA when i use "Makecode" to see the commnad often i get something with the unk in the description, red coxe xref and i think it's IDA's way to tell me that was expecting something in the first 64K but they are in the 2nd slice.
How i can tell IDA to take in charge the fact the bios has been slipt into two?