red-ray wrote on 2025-05-21, 22:03:All these are Xeon (Pentium 4) rather than Pentium !!! Xeon
Sorry, no affinity...
[attachment=-1]P3XEONnotes.txt[/attachment]
These three S-Specs were listed in an Intel product document dated june 17, 2004:
SL65C / RB80526PY800256SL65C
SL6HR / RK80530PZ017256SL6HR
SL6HS / RK80530PZ014256SL6HS
They can thus be classified as 'real' but the CPUID and stepping info is missing so not very useful I suppose.
Are you going to enter bga 479 or micro-bga2 495 packages into SIV ?
PARKE wrote on 2025-05-25, 09:56:Are you going to enter bga 479 or micro-bga2 495 packages into SIV ?
Without the CPUID S-Specs are of no use to SIV. I am not sure what you are asking, SIV will/should report bga 479, etc. I have no plans to add this to the S-Spec tables.
BTW I have a QHF3QS CPUID 6B1 Stepping A1 which I added, you don't seem to have an ES/QS S-Specs at the moment.
red-ray wrote on 2025-05-25, 10:43:I am not sure what you are asking, SIV will/should report bga 479, etc. I have no plans to add this to the S-Spec tables.
BTW I have a QHF3QS CPUID 6B1 Stepping A1 which I added, you don't seem to have an ES/QS S-Specs at the moment.
Are the S-Specs for the P2/3 cpu's the only ones or are they the only ones that produced anomalies ?
No, I always skipped ES & QS because they did not occur in the Intel documentation.
PARKE wrote on 2025-05-25, 13:24:Are the S-Specs for the P2/3 cpu's the only ones or are they the only ones that produced anomalies ?
SIV has S-Specs from i486 through to Pentium 4 (Northwood) including P2+P3 Xeon, but not P4 Xeon, 1026 in total. I don't recall any anomalies other than the P-3 ones, but suspect there are.
i486 is quite tricky as it seems Intel never released a public S-Spec update.
red-ray wrote on 2025-05-25, 13:55:SIV has S-Specs from i486 through to Pentium 4 (Northwood) including P2+P3 Xeon, but not P4 Xeon, 1026 in total. I don't recall any anomalies other than the P-3 ones, but suspect there are.
I came across one in a small list of extreme cpu's I made years ago:
red-ray wrote on 2025-05-25, 13:55:SIV has S-Specs from i486 through to Pentium 4 (Northwood) including P2+P3 Xeon, but not P4 Xeon, 1026 in total.
And you are not going to expand to later cpu's ?
PARKE wrote on 2025-05-25, 14:23:And you are not going to expand to later cpu's ?
IDK, time will tell, but as Intel no longer seem to release public S-Spec updates I doubt I will add many more.
I think that most if not all of them can still be found on-line.
Just for example:
30056103.pdf Intel Pentium 4 Processor on 90 nm Process Datasheet - feb 2005
30235231.pdf Intel Pentium 4 Processor 90 nm Process Specification Update - sep 2005
30638203.pdf Intel Pentium 4 Processor + Extreme Edition Datasheet - nov 2005
31559327.pdf Intel Core 2 Extreme Quad 6000 Specification Update - dec 2010
31872725.pdf Intel Core 2 Extreme Processor QX9000 Specification Update - dec 2011
32012104.pdf Intel® Core™2 Extreme Quad-Core MobileSpecification Update - nov 2008
Maybe, but Google can't find them https://www.google.com/search?q=intel+%2231872725%22
If searching via the pdf does not work you can try it differently, like on the text part :
Intel Core 2 Extreme Processor QX9000 Specification Update
which over here brings me directly to the Intel download site
https://www.intel.com/content/dam/www/public/ … spec-update.pdf
red-ray wrote on 2025-05-29, 11:38:It also has 0680 which AFAIK is a Coppermine SL3US.
I just found a BIOS with CPU µCode for the SL3US, there is also µCode for the CPUID 0680 Cascades 256KB
Does the SL46R has stepping B0 ?
Not sure what to do with your info on Cascades.
PARKE wrote on 2025-05-29, 12:34:Does
theSL46Rhashave stepping B0 ?
Reading The Wonky Manual it says B0, but it also says Mendocino when CPUID 0683 is Coppermine !
I just added SL46R and SIV whinged about your SSpec.tsv not having B0, please may I have the latest .TSV?, hopefully SIV will report less.
For your amusement.
Could not find the spec update 250721 for Mobile Pentium 4-M.
PARKE wrote on 2025-05-29, 14:08:For your amusement.
I am not amused! The check column is missing, why?, further there are no P-II + P-III CPUs
Checked 624 entries from D:\SIV\SSpec.tsv in 0.015 seconds, found 151 issues, 0 undated, 473 + 527 missing (100 Xeons) and skipped 0
red-ray wrote on 2025-05-29, 14:20:PARKE wrote on 2025-05-29, 14:08:For your amusement.
I am not amused! The check column is missing, why?, further there are no P-II + P-III CPUs
Checked 624 entries from D:\SIV\SSpec.tsv in 0.015 seconds, found 151 issues, 0 undated, 473 + 527 missing (100 Xeons) and skipped 0
Why aren't you amused ?
These are new P4 s-specs that I picked up last week. There is nothing in the check column - I only included columns with relevant info.
What are 473 and 527 ?
red-ray wrote on 2025-05-29, 12:59:I just added SL46R and SIV whinged about your SSpec.tsv not having B0, please may I have the latest .TSV?, hopefully SIV will report less.
I have not changed anything regarding the twenty one "issue" entries and I still do not have a B0.
PARKE wrote on 2025-05-29, 15:35:Why aren't you amused ?
The columns are different so I need different parsing code for no good reason. As a specified the P2 + P3 missing.
Ok, got it. I will soon send a complete update in the same format as the one that worked earlier for you but first I have to check what that format was - I may have changed something in y main file.
