butjer1010 wrote on 2026-01-23, 17:39:
This is the screen when it won't work 😀
Oh, this picture is actually very interesting. Yesterday I drafted an elaborate response how this might look like video memory address bits leaking into video data bits, but the specific pattern you are seeing does not match the EGA architecture at all, but I lost that draft response when inadvertantly closing the browser window, and I re-considered whether this information is relevant to the thread at all, and decided to not re-write it. Today, I read more details of the P82C435/P82A436 data sheet, and actually the pattern very much matches what would happen if the memory data bus A is not driven by the RAM chips during CRTC reads! The P82C435 multiplexes memory addresses and data over the same pins (which is not done at all in the original IBM EGA design), and the character and attribute codes seen in that screenshot exactly match the row addresses driven on the multiplexed pins before the read happens. On the other hand, font reads work perfectly (they happen on memory bus B).
In 80-character text mode, the EGA scan-out logic cards needs every opportunity to access video memory, and fetches a character code and a attribute byte (on bus A) for one character while fetching the pixel data for the previous character (on bus B) all at the same time. This is true for both the original IBM EGA card and the 82c435 integrated EGA controller. As all characters and attributes are wrong, while all font accesses are working, the issue can not be a mismatch between the "high/low CRT bandwidth setting" and the divide-by-2 setting, which could be a symptom if the mode is incompletely programmed into the EGA card. Furthermore, the signal to enable reading of character codes on memory bus A is the same signal as the one used to enable reading font data on memory bus B, it's /OE02 on pin 23 of the 82c435, and as font reads obviously work, the signal /OE02 obviously works, too. I don't see a reason why a card designer would want to add logic that prevents /OE02 to reach character memory (and /OE13 to reach attribute memory), but still allows /OE02 to reach font memory. So maybe the theory of missing /OExx on memory bus A is wrong? Except for /OE, there are two other signals that need to be active for attribute and character memory to respond, which are /RAS and /CAS. If any of /RAS, /CAS or /OE are missing on memory bus A, the screenshot you showed could be explained, but all of these signals are shared between memory busses A and B. So this seems like a dead end.
On the other hand, I have no idea what the empty positions U18..U25 are supposed to be for, as well as the logic chips U7 to U9. The datasheet of the EGA chipset claims that the chip count for an EGA card based on the 82C435/82A436 is just 13, which will be the two core ASICs, the BIOS chip, the monitor output driver chip U3 and the multiplexer chip U2, as well as 8 RAM chips. So the extra logic chips are something STB added to this design for some unknown purpose. Taking an educated guess, it looks like U18-U25 can take another 256KB of video memory for a total of 512KB. also, X1 and X3 could take extra clock generators for modes like 640x480 or 800x600. The EGA chipset used on that card is fast enough to handle those modes if given a sufficiently fast clock. It thus seems your PCB is designed for Super EGA operation, including the option of 512KB, which would provide two pages of video memory even at 800*600, yet only the chips required for standard EGA operation are provided. The three extra logic chips are used for video memory bank selection, and suddenly stuff starts to make some sense. What if memory bus A and memory bus B can be switched individually between the populated standard RAM or the "missing" extension RAM? If memory bus A would be switched to the extension RAM, the screen shot would be perfectly explainable! U8 is a dual flip-flop chip, which can be used to store two bank select bits. U9 is a quadruple OR chip, which can be used to gate four active-low signals (like /RAS or /CAS). This means U8/U9 are perfectly suited to implement bank switching. I can't easily guess what U7 (a 6-bit inverter) might be used for, though.
So, in essence, this means that the broken text mode picture you show would be explainable by a perfectly working EGA card with the bank selection not being properly initialized. It would be easy for the card designer to connect the CLEAR or PRESET pins of the 74LS74 to some RESET signal (e.g. the one on the ISA bus) to make sure the card starts with bus A and B switched to "standard memory", and I would expect this card to be implemented that way. So the "broken text" picture you show might point to a fault in the bank switch logic, and in that case, it is likely not related to Prince of Persia freezing. Well... Are you sure the computer freezes, or does only the image freeze, and you can continue playing blindly? If you can continue blindly, maybe the bank switching logic inadvertantly switched to a mode in which the computer starts updating the extension memory (which isn't there), while the card still displays the standard memory (which will no longer be updated). If that is the case, the "freezing" might also be due to a fault in the bank switching logic!
So indeed, U7 to U9 are possible suspects, and very common standard LS-TTL chips. Socketing and swapping them may in fact fix the card.
Deunan wrote on 2026-01-24, 09:55:
Other than the two ASICs there is just a handful of 74LS chips. But those do die in weir way, being bipolar based. With good soldering equipment and skills it might be worth socketing and replacing those. The '244 near monitor connector can stay, all it should do is drive the video signal out. The others are potentially suspect.
I suggest to include U2 to the "most likely not guilty" list as well. U2 is a dual 1-out-of-4 multiplexer, which is used to select one out of 4 clocks (only two of them used on a standard EGA), and one out of 4 DIP switches. If U2 fails on the clock half, you will no longer have an image, but as it seems, this card always produces a stable image, even if it fails. If U2 fails on the DIP switch half, the BIOS would have trouble reading the configuration switches, but that part is no longer relevant after POST. A failure of U2 is very unlikely to cause freezes with a stable image during a running system.