AngryByDefault wrote on 2024-11-06, 18:14:Hi, could you elaborate on that bit, @dionb?
This 'density' issue is very interesting to me because of how difficult to understa […]
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dionb wrote on 2024-11-06, 15:48: [...]so probably here there is also an issue with the address lines to the chipset[...]
Hi, could you elaborate on that bit, @dionb?
This 'density' issue is very interesting to me because of how difficult to understand it seems, perhaps because it's complexity causes the information always missing something out.
Thank you.
There's nothing complex about the density part so long as people stop vague "high" and "low" nonsense. A memory controller supports a certain density of memory chips. You can (or should be able to) look up what density is supported in the datasheet of the device.
The datasheet of the i430TX chipset is clear on the matter:
https://web.archive.org/web/20080224042728/ht … ts/29055901.pdf
The DRAM interface supports 4 Mbytes to 256 Mbytes with six RAS lines. The MTXC supports 4-Mbit, 16-Mbit,
and 64-Mbit DRAM and SDRAM technology,
So 64Mb chips are the highest officially supported. That means a 64MB DIMM with 8 chips of 64Mb each is explicitly supported.
But... your 64MB DIMM with 64Mb chips is being detected as a 16MB DIMM, as if it contained 16Mb chips. That means something is wrong. That means going a level deeper. To address the 64Mb chips requires 14 address lines, where 16Mb chips could be addressed with just 12. Now, reading the datasheet description of the memory interface I see this:
Note: For 64Mbit SDRAM support, BA1/MA12 and MA13 are muxed with the
RAS4# and RAS5# signals, respectively. When SDRAMC[bit 1]=1, BA1 and MA13
are driven out on these lines.
So the chipset only has 12 physical address lines and multiplexes MA12 and MA13 signals onto two of the RAS lines (RAS4 and 5), controlled by SDRAMC, the SDRAM controller.
Looking a bit further at the SDRAM controller I see this in the SDRAM control register:
64-Mbit Technology Enable (64MTEN). 1=Enable. 0=Disable. When set to 0, the MTXC does not
support 64-Mbit SDRAM devices. In this […]
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64-Mbit Technology Enable (64MTEN). 1=Enable. 0=Disable. When set to 0, the MTXC does not
support 64-Mbit SDRAM devices. In this mode, the MTXC supports 4-Mbit, 16-Mbit, and 64-Mbit
technology for EDO/FPM systems and 4 Mbit and 16 Mbit for SDRAM systems (i.e., 64 Mbit not
supported in SDRAM systems). When set to 1, the MTXC supports 4 Mbit, 16 Mbit, and 64 Mbit
for both SDRAM and EDO/FPM devices. In this mode, the RAS#/CS5# signal becomes
RAS#/CS5#/MA13, RAS4#/CS4# becomes RAS4#/CS4#/BA1, and KRQAK/CS4_64# becomes
CS4_64#. CS4_64# (fifth row) function is provided if this signal is set to 1 and DRAM Cache is not
present in the system (indicated by a 0 in bit 5, register 53h)
So, we have a couple of ways in which this might go wrong:
- the board happily supports 64Mb in hardware, but the 64MTEN register isn't being set (by BIOS)
- the board lacks the ability to demux MA12 and MA13 into separate address lines to the RAM (never seen this, but possible)
- the board has all correct hardware and software, but the traces of MA12 and/or MA13 are damaged.
Now, the motherboard manual says:
Die Hauptplatine unterstützt in den DIMM-Sockeln Module der Größen 8 MB, 16 MB, 32 MB und 64
MB
So 64MB DIMMs are explicitly supported, and that implies 64Mb chip density support, as there's no way to get to 64MB using 16Mb chips within spec (x64 per bank)
That means that it's unlikely to be lack of hardware support for demux - although this is PC Chips and I wouldn't put it past them to cut corners there and brazenly ignore that in the manual...
Given that point, I dug a bit deeper into the "Intel 430TX PCIset Desktop Design Guide":
https://theretroweb.com/chipset/documentation … f0398505276.pdf
Here I see:
64-Mbit SDRAM Support—This feature is supported on A-1 MTXC. A-0 MTXC does not support
64-Mbit SDRAM.
This refers to the stepping of the FC82439TX northbridge. A-0 does not support 64Mb SDRAM, A-1 does. Problem: I've not found any way to identify which stepping your chip has...
If it's the old one, it's game over.
Edit: found it - https://www.cpu-world.com/sspec/SL/SL238.html
A-1 stepping has SL-code SL238. A-0 steppings were only used in engineering samples (Qxxx instead of SLxxx)
DIMM wiring guideline
•• Connect MA11/BA0 to pin 122 of DIMM (BA0 for SDRAM, A11 for EDO/FPM)
•• Connect RAS4#/CS4#/BA1 to pins […]
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DIMM wiring guideline
•• Connect MA11/BA0 to pin 122 of DIMM (BA0 for SDRAM, A11 for EDO/FPM)
•• Connect RAS4#/CS4#/BA1 to pins 39 and 126 of DIMM (BA1, A12 for SDRAM, A12 for
EDO/FPM)
•• Connect RAS5#/CS5#/MA13 to pin 123 of DIMM (A11 for SDRAM, A13 for EDO/FPM)
Those are specifically the traces you should be checking for damage. If those A12/A13 pins aren't being fed correctly that could explain a thing or two.
Apart from that - is there a newer BIOS version available? If it's a register not being set, that could fix.
