I thought I'd post some direct comparing of EGA documentation and VGA bit register incompatibilities I've found by comparing the register descriptions. Nice for emulator authors still working on EGA emulation (that have VGA documentation) and generic stuff I've found out that's not always documented correctly everywhere:
on EGA:
SEQ clocking mode(0x01), bits 4(S4) and S5 (SD) unsupported. bit 1(bandwidth) added.
Character map(0x03) bits 4/5 (character map bits 2) unsupported
Extra note: SLR (bit 2 and S4 on VGA) affects loading of the latches! Usually zeroed, but can be used for multibyte rotation (ROL) of latched data, as proven by demos!
SEQ memory mode Chain 4 unsupported. Extended memory enables MA14/MA15.
CRTC horizontal total (00) is +2 instead of +5.
Extra note: CRTC hotizontal display enable end (01) is the last clock of active display (inclusive).
Extra note: End horizontal blanking register (03), bits 5/6(skew) is added to horizontal display enable end (register 01h) too, affecting both start and end of active display. Is 1 in 40-column modes.
EVRA isn't used on EGA and always active?
End horizontal retrace (05): bits 5-6 are added to retrace start. bit 7 is not End Horizontal Blanking bit 5(4-bit on EGA) and instead added to the memory address for the first pixel of every non-splitscreen (splitscreen being base 0) window scanline address on EGA!
Overflow (07) bit 5 is 'Cursor location bit 8'? It's VGA vertical total bit 9. bits 6-7 unsupported on EGA.
Luckily preset row scan(08) 'byte panning' doesn't exist, preventing conflicts with MA0 being 0/1 for the first pixel.
Maximum scanline register(09) doesn't implement scan doubling (bit 7). bits 5-6 unsupported.
Cursor start(0A) bit 5 unsupported. Perhaps in overflow register(07) bit 5 instead?
Vertical retrace end (11) bit 7 unsupported on EGA. Bit 6 is unused on EGA.
Underline location(14) bits 5/6 don't exist.
End vertical blanking(16) 5-bits (EGA) instead of 7-bits(VGA).
Mode control (17) bit 4 (EGA-only) forces the module 'output drivers' to high-impedance state?
Graphics controller:
Graphics 1 position (3CC w/o) and Graphics 2 position (3CA w/o). 1 must be 0 and 2 must be 1. unknown behaviour of setting. registers are a 2-bit binary number.
Read map select (04) is a 3-bit (EGA) instead of 2-bit(VGA) binary value?
Mode register(05): write mode 3 'Not Valid' on EGA. Real behaviour unknown if used. bit 2 puts outputs in high impedence state on EGA.
Attribute controller:
3C1 writes perform writes to 3C0 on EGA.
- Interesting, EGA documentation swaps bit layout tables of the index registers with the palette (00-0F) registers.
mode control(10): bits 5-7 not implemented on EGA (pixel panning forced as if 0 on EGA?). EGA MONO bit really affects attributes and graphics mode(adds mask 0x05 on top of color plane enable and special C0/C2 behaviour in graphics modes?).
Overscan color(11) only 6-bit on EGA and might work in monochrome monitors (using 0,8,10h,18h for intensities) although adviced zeroed to make it black?
Color plane enable(12) has additional bits 4-5 (video status MUX) on EGA required to POST. This outputs 0 in Input Status 1 without display enable.
Register 14h (color select register) doesn't exist on EGA.
DAC color registers don't exist on EGA.
Misc Output bit 4 on EGA drives color output from the feature connector instead of attribute controller. bit 5(page bit) might be inversed for both EGA and VGA?
Input Status 0 register: bits 5-6 are binary numbers from the feature connector. Their inputs for either FC0 set (lower bits) and FC1 set (higher bits) are loaded into the BIOS byte containing the switches(it's upper 4 bits). The Switch Sense bit number on VGA is obtained from the misc output register Clock Select. On EGA, the switch number (SW1-SW4) is REVERSED, so Clock Select 0 selects SW4 and Clock Select 3 selects SW1. bit 7 on EGA indicates active display(1) or (vertical?) retrace (0)? Is this inversed bit 4 of register 1 or the display enable signal itself? It documents as 'CRT interrupt'. Is this related to vertical retrace end(CRTC 11) bits 4 and 5? Perhaps set by bit 4 and cleared on retrace when bit 5 is set? Drives IRQ (2 or 9 depending on motherboard) inversed?
Input status 1 register: bit 1 indicates light pen trigger set. bit 2 indicates light pen switch is open (not pressed?). Bits 4-5 report video status MUX (see color plane enable register) on EGA, required to POST.