Reply 60 of 71, by Jepael
wrote:Yes, it is. I think so. Thank you!
Now I'll check DB50 and SW60 about 4/8FS SEL to see its connecting to ground (or not). And then will think how to connect DIT4096. If DIT4096 needs Master Clock Signal it is necessary to find it on XQ036AO chip.
Looking at DB50XG pictures, it's not connected to GND. It could be supply voltage, or, it could be floating, and I can't read from the datasheet if the 4/8FS SEL pin has internal pull-up or pull-down.
On the other hand, there are four wires coming from the DAC, to pins CLK, SI/LSI, LRSEL/RSI, LRCK/WDCK, which would appear that it uses two data wires. Otherwise it would use only three.
And yes, the DIT4096 needs a MCLK (as they almost always do), that is either 256x, 384x or 512x Fs. Based on the 33.868 MHz crystal on board, it is 44100*768, so there is a good chance there is a 384xFs clock available, or you can easily divide one from the 33.868 MHz clock. Another chance would be to generate MCLK from bit clock, or even left/right clock, with a PLL.
Edit: Found a SW60XG picture, it shows both 4/8FS SEL and 16/18BIT selection are connected to VDD.