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First post, by superfury

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What is the state when, for example, a single-step exception throws an exception? What is the state of registers in the causative task that has TF set? What about it's memory and register state(EIP, EFLAGS, memory accesses done by the instruction)?

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Reply 1 of 4, by Stenzek

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As far as I understand it, it's the same as a regular exception, except the IP pushed on the stack is after the instruction, not before.

Edit: Not sure about the EXT bit, though. Would have to check.

Reply 2 of 4, by superfury

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It's probably set, as the debug fault isn't triggered by the instruction at CS:(E)IP itself? Thus external?

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Reply 4 of 4, by superfury

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What about the DR6 bits? Are they still going to be set during the double fault(#DB+exception=double fault)? Or are they only applied at the end of a succeeding #DB exception(when it commits the exception handler for the next instruction), instead of pushing the error code?

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