maxtherabbit wrote on 2023-05-10, 17:47:
I wasn't referring to bus transceivers. More like gating the memory read/write strobes from ever going active on the ISA slots if the onboard memory is serving the access.
So, I got around to check the IBM schematics. Contrary to my previous post, there is no I/O steering. All I/O and memory read and writes reach the ISA bus. But most of the on-board components (ROMs, DMAC, PIT, PIC, keyboard interface) are located on the X-Bus which is connected to the ISA bus using a 74LS245 transceiver (U13). This transceiver is enabled on every bus cycle. The "direction" signal of this transceiver is "from X-bus to ISA bus" for memory reads from F000-FFFF and for I/O reads from 000..1FF (and all aliases). This occupies the ISA bus for the F segment and the low half of the PC I/O space.
The RAM is also connected using a transceiver from the memory data bus to the ISA bus (U12). This transceiver is enabled for access to the first 64K of address space, and transfers towards the ISA bus for all memory reads.
So for the original 5150 mainboard, you can not provide readable resources on the first 64K memory, the last 64K memory and I/O addresses with A9 clear, because that will fight transceivers on the mainboard. I suspect the 64K-256K 5150 board and the 5160 board to contain similar logic, but decoding the low 256K instead of the low 64K for onboard RAM.