| |
|
| [General Information]
|
| Processor Name: | AMD Athlon-806
|
| Current Processor Frequency: | 805.7 MHz
|
| Current Processor Frequency [MHz]: | 806
|
| | |
|
| CPU ID: | 00000622
|
| Extended CPU ID: | 00000722
|
| CPU Brand Name: | AMD Athlon(tm) Processor
|
| CPU Vendor: | AuthenticAMD
|
| CPU Stepping: | A2
|
| CPU Code Name: | Pluto
|
| CPU Technology: | 180 nm
|
| CPU Platform: | Slot A (SECC-242)
|
| | |
|
| Number of CPU Cores: | 1
|
| Number of Logical CPUs: | 1
|
| | |
|
| [Operating Points]
|
| CPU Current: | 805.7 MHz = 8.00 x 100.7 MHz
|
| | |
|
| CPU Bus Type: | FSB (DDR)
|
| | |
|
| [Cache and TLB]
|
| L1 Cache: | Instruction: 64 KBytes, Data: 64 KBytes
|
| L2 Cache: | Integrated: 512 KBytes
|
| Instruction TLB: | Fully associative, 16 entries
|
| Data TLB: | Fully associative, 24 entries
|
| | |
|
| [Standard Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| Pentium-style Model Specific Registers | Present
|
| Physical Address Extension | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip / PGE (AMD) | Not Present
|
| Fast System Call | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Processor Number | Not Present
|
| CLFLUSH Instruction | Not Present
|
| Debug Trace and EMON Store | Not Present
|
| Internal ACPI Support | Not Present
|
| MMX Technology | Present
|
| Fast FP Save/Restore (IA MMX-2) | Present
|
| Streaming SIMD Extensions | Not Present
|
| Streaming SIMD Extensions 2 | Not Present
|
| Self-Snoop | Not Present
|
| Multi-Threading Capable | Not Present
|
| Automatic Clock Control | Not Present
|
| IA-64 Processor | Not Present
|
| Signal Break on FERR | Not Present
|
| Streaming SIMD Extensions 3 | Not Present
|
| PCLMULQDQ Instruction Support | Not Present
|
| MONITOR/MWAIT Support | Not Present
|
| Supplemental Streaming SIMD Extensions 3 | Not Present
|
| FMA Extension | Not Present
|
| CMPXCHG16B Support | Not Present
|
| Streaming SIMD Extensions 4.1 | Not Present
|
| Streaming SIMD Extensions 4.2 | Not Present
|
| x2APIC | Not Present
|
| POPCNT Instruction | Not Present
|
| AES Cryptography Support | Not Present
|
| XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Not Present
|
| XGETBV/XSETBV OS Enabled | Not Present
|
| AVX Support | Not Present
|
| Half-Precision Convert (CVT16) | Not Present
|
| [Extended Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| AMD-style Model Specific Registers | Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip | Not Present
|
| SYSCALL and SYSRET Instructions | Present
|
| Memory Type Range Registers | Present
|
| Page Global Feature | Present
|
| Machine Check Architecture | Present
|
| CMOV Instruction | Present
|
| Page Attribute Table | Present
|
| 36-bit Page Size Extensions | Present
|
| Multi-Processing / Brand feature | Not Present
|
| No Execute | Not Present
|
| MMX Technology | Present
|
| MMX+ Extensions | Present
|
| Fast FP Save/Restore | Present
|
| Fast FP Save/Restore Optimizations | Not Present
|
| 1 GB large page support | Not Present
|
| RDTSCP Instruction | Not Present
|
| x86-64 Long Mode | Not Present
|
| 3DNow! Technology Extensions | Present
|
| 3DNow! Technology | Present
|
| LAHF/SAHF Long Mode Support | Not Present
|
| Core Multi-Processing Legacy Mode | Not Present
|
| Secure Virtual Machine | Not Present
|
| Extended APIC Register Space | Not Present
|
| LOCK MOV CR0 Support | Not Present
|
| Advanced Bit Manipulation | Not Present
|
| SSE4A Support | Not Present
|
| Misaligned SSE Mode | Not Present
|
| PREFETCH(W) Support | Not Present
|
| OS Visible Work-around Support | Not Present
|
| Instruction Based Sampling | Not Present
|
| XOP Instruction Support | Not Present
|
| SKINIT, STGI, and DEV Support | Not Present
|
| Watchdog Timer Support | Not Present
|
| TBM0 Instruction Support | Not Present
|
| Lightweight Profiling Support | Not Present
|
| FMA4 Instruction Support | Not Present
|
| Translation Cache Extension | Not Present
|
| NodeId Support | Not Present
|
| Trailing Bit Manipulation | Not Present
|
| Topology Extensions | Not Present
|
| Core Performance Counter Extensions | Not Present
|
| NB Performance Counter Extensions | Not Present
|
| Streaming Performance Monitor Architecture | Not Present
|
| Data Breakpoint Extension | Not Present
|
| Performance Time-Stamp Counter | Not Present
|
| L2I Performance Counter Extensions | Not Present
|
| MWAITX/MONITORX Support | Not Present
|
| Secure Memory Encryption | Not Present
|
| Secure Encrypted Virtualization | Not Present
|
| | |
|
| [Enhanced Features]
|
| Core Performance Boost | Not Supported
|
| | |
|
| [Memory Ranges]
|
| Maximum Physical Address Size: | 36-bit (64 (null))
|
| Maximum Virtual Address Size: | 32-bit (4 (null))
|
| [MTRRs]
|
| Range 0-10000000 (0MB-256MB) Type: | Write Back (WB)
|
| |
|
| [General Information]
|
| Device Name: | VIA VT82C686A PCI-to-ISA Bridge
|
| Original Device Name: | VIA VT82C686A PCI-to-ISA Bridge
|
| Device Class: | PCI-to-ISA Bridge
|
| Revision ID: | 1B
|
| PCI Address (Bus:Device:Function) Number: | 0:4:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1106&DEV_0686&SUBSYS_800D1043&REV_1B
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | VIA
|
| Driver Description: | VIA PCI to ISA bridge
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_0686&SUBSYS_00000000&REV_1B\2&EBB567F&0&20
|
| | |
|
| [ISA Bus Control]
|
| ISA Command Delay: | Normal
|
| Extended ISA Bus Ready: | Disabled
|
| ISA Slave Wait States: | 4 WS
|
| Chipset I/O Wait States: | 2 WS
|
| I/O Recovery Time: | Enabled
|
| Extended ALE: | Disabled
|
| ROM Wait States: | 1 WS
|
| ROM Writes: | Disabled
|
| | |
|
| [ISA Test Mode]
|
| Bus Refresh Arbitration: | Disabled
|
| XRDY Test Mode: | Disabled
|
| Fast Reset Via PORT 92h: | Disabled
|
| A20G Emulation: | Disabled
|
| Double DMA Clock: | 1/2 ISA clock
|
| SHOLD Lock During INTA: | Disabled
|
| Refresh Request Test Mode: | Disabled
|
| ISA Refresh: | Enabled
|
| | |
|
| [ISA Clock Control]
|
| Latch IO16#: | Enabled
|
| MS16# Output: | Enabled
|
| Master Request Test Mode: | Disabled
|
| ISA Bus Clock Select: | Disabled (=PCLK/4)
|
| ISA Bus Clock: | PCICLK/3
|
| | |
|
| [ROM Decode Control]
|
| 64K ROM At FFFE00000h-FFFEFFFFh: | Disabled
|
| 384K ROM At FFF80000h-FFFDFFFFh: | Disabled
|
| 32K ROM At E8000h-EFFFFh: | Disabled
|
| 32K ROM At E0000h-E7FFFh: | Disabled
|
| 32K ROM At D8000h-D8FFFh: | Disabled
|
| 32K ROM At D0000h-D7FFFh: | Disabled
|
| 32K ROM At C8000h-CFFFFh: | Disabled
|
| 32K ROM At C0000h-C7FFFh: | Disabled
|
| | |
|
| [Keyboard Controller Control]
|
| KBC Timeout Test: | Disabled
|
| Mouse Lock: | Disabled
|
| | |
|
| [Type F DMA Control]
|
| ISA Master/DMA To PCI Line Buffer: | Enabled
|
| Type F Timing On DMA Channel 7: | Disabled
|
| Type F Timing On DMA Channel 6: | Disabled
|
| Type F Timing On DMA Channel 5: | Disabled
|
| Type F Timing On DMA Channel 3: | Disabled
|
| Type F Timing On DMA Channel 2: | Disabled
|
| Type F Timing On DMA Channel 1: | Disabled
|
| Type F Timing On DMA Channel 0: | Disabled
|
| | |
|
| [Miscellaneous Control 1]
|
| PCI Master Write Wait States: | 0 WS
|
| Gate INTRQ: | Enabled
|
| Flush Line Buffer for Int or DMA IOR Cycle: | Enabled
|
| Config Command Register Test Mode: | Disabled
|
| Interruptions Of PCI Burst Reads: | Disallowed
|
| Posted Memory Writes: | Disabled
|
| | |
|
| [Miscellaneous Control 2]
|
| CPU Reset Signal: | INIT
|
| PCI Transaction Delay: | Enabled
|
| EISA Port 4D0h/4D1h: | Enabled
|
| Interrupt Controller Shadow Register: | Disabled
|
| Write Delay Transaction Time-out Timer: | Enabled
|
| Read Delay Transaction Time-out Timer: | Enabled
|
| | |
|
| [Miscellaneous Control 3]
|
| Extra RTC Port 74h/75h: | Disabled
|
| Integrated USB Controller: | Enabled
|
| Integrated IDE Controller: | Enabled
|
| 512K PCI Memory Decode: | Enabled
|
| | |
|
| [IDE Interrupt Routing]
|
| Wait For PGNT Before Grant to ISA Master/DMA: | Yes
|
| Port 0-FFh Bus Select: | Access via SD bus
|
| Secondary IDE Channel IRQ: | IRQ15
|
| Primary IDE Channel IRQ: | IRQ14
|
| | |
|
| [ISA DMA/Master Memory Access Control 1]
|
| PCI Memory Hole Bottom: | 0
|
| | |
|
| [ISA DMA/Master Memory Access Control 2]
|
| PCI Memory Hole Top: | 0
|
| | |
|
| [ISA DMA/Master Memory Access Control 3]
|
| Top Of PCI Memory For ISA DMA/Master Access: | 16 MBytes
|
| Access To E0000h-EFFFFh Forwarded To PCI: | Disabled
|
| Access To A0000h-BFFFFh Forwarded To PCI: | Disabled
|
| Access To 80000h-9FFFFh Forwarded To PCI: | Enabled
|
| Access To 00000h-7FFFFh Forwarded To PCI: | Enabled
|
| Access To DC000h-DFFFFh Forwarded To PCI: | Disabled
|
| Access To D8000h-DBFFFh Forwarded To PCI: | Disabled
|
| Access To D4000h-D7FFFh Forwarded To PCI: | Disabled
|
| Access To D0000h-D3FFFh Forwarded To PCI: | Disabled
|
| Access To CC000h-CFFFFh Forwarded To PCI: | Disabled
|
| Access To C8000h-CBFFFh Forwarded To PCI: | Disabled
|
| Access To C4000h-C7FFFh Forwarded To PCI: | Disabled
|
| Access To C0000h-C3FFFh Forwarded To PCI: | Disabled
|
| | |
|
| [PNP DMA Request Control]
|
| PnP Routing for Parallel Port: | DRQ3
|
| PnP Routing for Floppy: | DRQ2
|
| | |
|
| [PNP IRQ Routing 1]
|
| PnP Routing for Parallel Port: | Disabled
|
| PnP Routing for Floppy: | Disabled
|
| | |
|
| [PCI IRQ Polarity]
|
| PIRQA#: | Level-sensitive
|
| PIRQB#: | Level-sensitive
|
| PIRQC#: | Level-sensitive
|
| PIRQD#: | Level-sensitive
|
| | |
|
| [PnP IRQ Routing 4]
|
| PIRQA# Routing: | IRQ11
|
| | |
|
| [PnP IRQ Routing 5]
|
| PIRQC# Routing: | Disabled
|
| PIRQB# Routing: | Disabled
|
| | |
|
| [PnP IRQ Routing 6]
|
| PIRQD# Routing: | IRQ10
|
| | |
|
| [PCS0# Control]
|
| PCS0# Pin Function: | PCS0#
|
| | |
|
| [KBC / RTC Power-On Strap Options]
|
| Keyboard RP16: | Enabled
|
| Keyboard RP15: | Enabled
|
| Keyboard RP14: | Enabled
|
| Keyboard RP13: | Enabled
|
| Audio Function: | Enabled
|
| Internal RTC: | Enabled
|
| Internal PS/2 Mouse: | Enabled
|
| Internal Keyboard Controller: | Enabled
|
| | |
|
| [Internal RTC Test Mode]
|
| RTC Map Rx32 to Rx3F: | Enabled
|
| RTC Reset: | Disabled
|
| RTC SRAM Access: | Disabled
|
| RTC Test Mode: | Disabled
|
| | |
|
| [DMA Control]
|
| PCS0# & PCS1# 16-Bit I/O: | Disabled
|
| Passive Release: | Enabled
|
| Internal Passive Release: | Enabled
|
| Dummy PREQ: | Enabled
|
| External APIC Configuration: | External APIC on XD Bus
|
| DMA Line Buffer: | Enabled
|
| | |
|
| [Distributed DMA, Channel 0 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 1 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 2 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 3 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 5 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 6 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [Distributed DMA, Channel 7 Base/Enable]
|
| Base Address: | 0
|
| DMA Channel: | Disabled
|
| | |
|
| [GPIO Control 1]
|
| APIC Enable: | Disabled
|
| SERIRQ Pin: | SERIRQ input from DRQ2
|
| GPIOD Direction: | Output
|
| GPIOC Direction: | Input
|
| GPIOB Direction: | Input
|
| GPIOA Direction: | Output
|
| THRM: | GPI5
|
| GPI0/IOCHCK Select: | IOCHCK#
|
| | |
|
| [GPIO Control 2]
|
| GPO7 Enable: | SLP#
|
| GPO5 Enable: | PCISTP#
|
| GPO4 Enable: | CPUSTP#
|
| FDC External IRQ / DRQ Via DACK2# / DRQ2: | FDCIRQ, FDCDRQ
|
| GPO25 Enable: | DACK2#
|
| GPO24 Enable: | DRQ2/SERIRQ
|
| Decode: | Subtractive
|
| | |
|
| [GPIO Control 3]
|
| Over-Current (OC) Input: | Disabled
|
| OC[3:0] From SD[3:0] By Scan: | Disabled
|
| GPO14 / GPO15 Enable: | IRTX and IRRX
|
| PCS0# Enable: | Disabled
|
| MCCS# Enable: | GPIOD/GPI11/GPO11
|
| CHAS Enable: | GPIOC
|
| GPO12 Enable: | GPO12
|
| GPOWE# (GPO[23-16]) Enable: | GPIOA
|
| | |
|
| [GPIO Control 4]
|
| DRQ / DACK# Pins are GPI / GPO: | Disabled
|
| Game Port XY Pins are GPI / GPO: | Disabled
|
| SERIRQ SMI Slot: | Disabled
|
| RTC Rx32 Write Protect: | Disabled
|
| RTC Rx0D Write Protect: | Enabled
|
| GPO13 Enable: | SOE#
|
| | |
|
| [PCI DMA Channel Enable]
|
| PCI DMA Pair A: | Disabled
|
| PCI DMA Channel 7 Enable: | Disabled
|
| PCI DMA Channel 6 Enable: | Disabled
|
| PCI DMA Channel 5 Enable: | Disabled
|
| PCI DMA Channel 3 Enable: | Disabled
|
| PCI DMA Channel 2 Enable: | Disabled
|
| PCI DMA Channel 1 Enable: | Disabled
|
| PCI DMA Channel 0 Enable: | Disabled
|
| | |
|
| [32-Bit DMA Control]
|
| 32-Bit DMA High Page IOBase: | 0
|
| 32-Bit DMA: | Disabled
|
| | |
|
| [ISA Positive Decoding Control 1]
|
| On-Board I/O Port Positive Decoding: | Disabled
|
| MSS I/O Port Positive Decoding: | Disabled
|
| MSS I/O Decode Range: | 0530h-0537h
|
| APIC Positive Decoding: | Disabled
|
| BIOS ROM Positive Decoding: | Disabled
|
| PCS0 Positive Decoding: | Disabled
|
| | |
|
| [ISA Positive Decoding Control 2]
|
| FDC Positive Decoding: | Disabled
|
| LPT Positive Decoding: | Disabled
|
| LPT Decode Range: | 3BCh-3BFh, 7BCh-7BEh
|
| Game Port Positive Decoding: | Disabled
|
| MIDI Positive Decoding: | Disabled
|
| MIDI Decode Range: | 300h-303h
|
| | |
|
| [ISA Positive Decoding Control 3]
|
| COM Port B Positive Decoding: | Disabled
|
| COM Port B Decode Range: | 3F8h-3FFh
|
| COM Port A Positive Decoding: | Disabled
|
| COM Port A Decode Range: | 3F8h-3FFh
|
| | |
|
| [ISA Positive Decoding Control 4]
|
| FDC Decoding Range: | Primary
|
| Sound Blaster Positive Decoding: | Disabled
|
| Sound Blaster Decode Range: | 260h-26Fh, 270h-273h
|
| | |
|
| [Extended Function Enable]
|
| Function 3 USB Ports 2-3: | Disabled
|
| Function 6 Modem / Audio: | Enabled
|
| Function 5 Audio: | Enabled
|
| Super-I/O Configuration: | Disabled
|
| Super-I/O: | Enabled
|
| | |
|
| [PCS Control]
|
| PCS3# For Internal I/O: | Disabled
|
| PCS2# For Internal I/O: | Disabled
|
| PCS1# For Internal I/O: | Disabled
|
| PCS0# For Internal I/O: | Disabled
|
| PCS3#: | Disabled
|
| PCS2#: | Disabled
|
| PCS1#: | Disabled
|
| PCS0#: | Enabled
|
| | |
|
| []
|
| PCS2# I/O Port Address: | 0
|
| | |
|
| []
|
| PCS3# I/O Port Address: | 0
|
| |
|
| [General Information]
|
| Device Name: | VIA VT82C571 Integrated IDE Controller
|
| Original Device Name: | VIA VT82C571 Integrated IDE Controller
|
| Device Class: | IDE Controller
|
| Revision ID: | 6
|
| PCI Address (Bus:Device:Function) Number: | 0:4:1
|
| PCI Latency Timer: | 32
|
| Hardware ID: | PCI\VEN_1106&DEV_0571&SUBSYS_00000000&REV_06
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| I/O Base Address 4 | FFA0
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Capable
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | VIA Technologies, Inc.
|
| Driver Description: | VIA Bus Master IDE Controller
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_0571&SUBSYS_00000000&REV_06\2&EBB567F&0&21
|
| | |
|
| [Chip Enable]
|
| Primary IDE Channel: | Enabled
|
| Secondary IDE Channel: | Enabled
|
| | |
|
| [IDE Configuration I]
|
| Primary IDE Read Prefetch Buffer: | Enabled
|
| Primary IDE Post Write Buffer: | Enabled
|
| Secondary IDE Read Prefetch Buffer: | Enabled
|
| Secondary IDE Post Write Buffer: | Enabled
|
| | |
|
| [IDE Configuration II]
|
| PIO Operating Mode - Primary Channel: | Compatibility Mode
|
| PIO Operating Mode - Secondary Channel: | Compatibility Mode
|
| | |
|
| [FIFO Configuration]
|
| FIFO Configuration: | PRI = 8, SEC = 8
|
| Primary Channel FIFO Threshold: | 3/4
|
| Secondary Channel FIFO Threshold: | 3/4
|
| | |
|
| [Miscellaneous Control 1]
|
| Master Read Cycle IRDY# Wait State: | 0 WS
|
| Master Write Cycle IRDY# Wait State: | 0 WS
|
| FIFO Output Data 1/2 Clock Advance/PIO Read Pre-Fetch Byte Counter: | Disabled
|
| Bus-Master IDE Status Register Read Retry: | Enabled
|
| Packet Command Prefetching: | Disabled
|
| UltraDMA Host Must Wait for First Transfer Before Termination: | Enabled
|
| | |
|
| [Miscellaneous Control 2]
|
| Interrupt Steering Swap Between Channels: | Disabled
|
| Rx3C Write Protect: | Enabled
|
| Memory-Read-Multiple Command: | Disabled
|
| Memory-Write-and-Invalidate Command: | Disabled
|
| | |
|
| [Miscellaneous Control 3]
|
| Read DMA FIFO Flush (PRI): | Enabled
|
| Read DMA FIFO Flush (SEC): | Enabled
|
| End-of-Sector FIFO Flush (PRI): | Disabled
|
| End-of-Sector FIFO Flush (SEC): | Disabled
|
| Maximum DRDY# Pulse Width: | Unlimited
|
| | |
|
| [Drive Timing Control]
|
| Primary Drive 0 Active Pulse Width: | 3 clocks
|
| Primary Drive 0 Recovery Time: | 1 PCICLKs
|
| Primary Drive 1 Active Pulse Width: | 11 PCICLKs
|
| Primary Drive 1 Recovery Time: | 9 clocks
|
| Secondary Drive 0 Active Pulse Width: | 11 clocks
|
| Secondary Drive 0 Recovery Time: | 9 PCICLKs
|
| Secondary Drive 1 Active Pulse Width: | 11 PCICLKs
|
| Secondary Drive 1 Recovery Time: | 9 clocks
|
| | |
|
| [Address Setup Time]
|
| Primary Drive 0 Address Setup Time: | 4T
|
| Primary Drive 1 Address Setup Time: | 4T
|
| Secondary Drive 0 Address Setup Time: | 4T
|
| Secondary Drive 1 Address Setup Time: | 4T
|
| | |
|
| [Secondary Non-01F0h Port Access Timing]
|
| DIOR#/DIOW# Active Pulse Width: | 16 PCICLKs
|
| DIOR#/DIOW# Recovery Time: | 16 PCICLKs
|
| | |
|
| [Primary Non-01F0h Port Access Timing]
|
| DIOR#/DIOW# Active Pulse Width: | 16 PCICLKs
|
| DIOR#/DIOW# Recovery Time: | 16 PCICLKs
|
| | |
|
| [Ultra-DMA Extended Timing Control (SEC DRV 1)]
|
| Ultra-DMA Mode Enable Method: | Using Set Feature Cmd.
|
| Ultra-DMA Mode: | Disabled
|
| Transfer Mode: | DMA or PIO
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 5T
|
| | |
|
| [Ultra-DMA Extended Timing Control (SEC DRV 0)]
|
| Ultra-DMA Mode Enable Method: | Using Set Feature Cmd.
|
| Ultra-DMA Mode: | Disabled
|
| Transfer Mode: | DMA or PIO
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 5T
|
| | |
|
| [Ultra-DMA Extended Timing Control (PRI DRV 1)]
|
| Ultra-DMA Mode Enable Method: | Using Set Feature Cmd.
|
| Ultra-DMA Mode: | Disabled
|
| Transfer Mode: | DMA or PIO
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 13T
|
| | |
|
| [Ultra-DMA Extended Timing Control (PRI DRV 0)]
|
| Ultra-DMA Mode Enable Method: | Using this reg.
|
| Ultra-DMA Mode: | Enabled
|
| Transfer Mode: | Ultra-DMA
|
| Cable Type Reporting: | 40-pin
|
| Drive Cycle Time: | 2T
|
| | |
|
| [Ultra-DMA FIFO Control]
|
| Lower ISA Request Priority When Write Device Packet Command is Issued: | Disabled
|
| Clear Native Mode Interrupt on Falling Edge of Gated Interrupt: | Disabled
|
| Improve PIO Prefetch and Post-Write Performance: | Disabled
|
| Memory Prefetch Size: | 1 line
|
| Change Drive Clears All FIFO & Internal States: | Enabled
|
| Complete DMA Cycle with Transfer Size Less Than FIFO Size: | Enabled
|
| | |
|
| [IDE Clock Gating]
|
| Dynamic 100/133 MHz Clock Gating: | Enabled
|
| Dynamic 66 MHz Clock Gating: | Enabled
|
| | |
|
| [Primary Sector Size]
|
| Sector Size: | 512 Bytes/Sector
|
| | |
|
| [Secondary Sector Size]
|
| Sector Size: | 512 Bytes/Sector
|
| |
|
| [General Information]
|
| Device Name: | VIA VT82C686A USB Universal Host Controller
|
| Original Device Name: | VIA VT82C686A USB Universal Host Controller
|
| Device Class: | USB UHCI Controller
|
| Revision ID: | E
|
| PCI Address (Bus:Device:Function) Number: | 0:4:2
|
| PCI Latency Timer: | 64
|
| Hardware ID: | PCI\VEN_1106&DEV_3038&SUBSYS_12340925&REV_0E
|
| | |
|
| [System Resources]
|
| Interrupt Line: | IRQ10
|
| Interrupt Pin: | INTD#
|
| I/O Base Address 4 | D400
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| USB Version Supported: | 1.0
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | VIA Technologies
|
| Driver Description: | VIA Rev 5 or later USB Universal Host Controller
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_3038&SUBSYS_12340925&REV_0E\2&EBB567F&0&22
|
| | |
|
| [Miscellaneous Control 1]
|
| PCI Memory Commands Support: | MRL, MRM, and MWAI
|
| Babbled Port of EOF: | Enabled
|
| PCI Parity Checking: | Disabled PERR#
|
| Frame Interval Select: | 1 msec
|
| USB Data Length Limit: | 1280 bytes
|
| USB Power Management/Improved FIFO Latency: | Disabled
|
| DMA Limited To: | 16-DW Burst
|
| PCI Wait States: | 0 WS
|
| | |
|
| [Miscellaneous Control 2]
|
| USB 1.1 Improvement for EOP: | Disabled (USB 1.0)
|
| Trap Status Bits Override: | Disabled
|
| A20GATE Pass Through Option: | Pass
|
| | |
|
| [Miscellaneous Control 4]
|
| Continue Transmission of Erroneous Data on FIFO Underrun: | Enabled
|
| Issue CRC Error Instead of Stuffing Error on FIFO Underrun: | Enabled
|
| | |
|
| [Miscellaneous Control 5]
|
| Issue Bad CRC5 in SOF After FIFO Underrun: | Enabled
|
| Lengthen PreSOF Time: | Enabled
|
| Issue Nonzero Bad CRC Code on FIFO Underrun: | Non zero CRC
|
| | |
|
| [Miscellaneous Control 6]
|
| EHCI Supports PME Assertion in D3 Cold State: | Not Supported
|
| UHCI Supports PME Assertion in D3 Cold State: | Not Supported
|
| | |
|
| [Miscellaneous Control 7]
|
| Use External 60 MHz Clock: | Disabled
|
| | |
|
| [USB Release Number]
|
| USB Release Number: | 1.0
|
| | |
|
| [USB Legacy Support]
|
| UHCI v1.1 Compliant: | 2000
|
| |
|
| [General Information]
|
| Device Name: | VIA VT82C686A USB Universal Host Controller
|
| Original Device Name: | VIA VT82C686A USB Universal Host Controller
|
| Device Class: | USB UHCI Controller
|
| Revision ID: | E
|
| PCI Address (Bus:Device:Function) Number: | 0:4:3
|
| PCI Latency Timer: | 64
|
| Hardware ID: | PCI\VEN_1106&DEV_3038&SUBSYS_12340925&REV_0E
|
| | |
|
| [System Resources]
|
| Interrupt Line: | IRQ10
|
| Interrupt Pin: | INTD#
|
| I/O Base Address 4 | D800
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| USB Version Supported: | 1.0
|
| | |
|
| [Driver Information]
|
| Driver Manufacturer: | VIA Technologies
|
| Driver Description: | VIA Rev 5 or later USB Universal Host Controller
|
| Driver Provider: | Microsoft
|
| Driver Version: | 5.1.2600.5512
|
| Driver Date: | 30-Jun-2001
|
| DeviceInstanceId | PCI\VEN_1106&DEV_3038&SUBSYS_12340925&REV_0E\2&EBB567F&0&23
|
| | |
|
| [Miscellaneous Control 1]
|
| PCI Memory Commands Support: | MRL, MRM, and MWAI
|
| Babbled Port of EOF: | Enabled
|
| PCI Parity Checking: | Disabled PERR#
|
| Frame Interval Select: | 1 msec
|
| USB Data Length Limit: | 1280 bytes
|
| USB Power Management/Improved FIFO Latency: | Disabled
|
| DMA Limited To: | 16-DW Burst
|
| PCI Wait States: | 0 WS
|
| | |
|
| [Miscellaneous Control 2]
|
| USB 1.1 Improvement for EOP: | Disabled (USB 1.0)
|
| Trap Status Bits Override: | Disabled
|
| A20GATE Pass Through Option: | Pass
|
| | |
|
| [Miscellaneous Control 4]
|
| Continue Transmission of Erroneous Data on FIFO Underrun: | Enabled
|
| Issue CRC Error Instead of Stuffing Error on FIFO Underrun: | Enabled
|
| | |
|
| [Miscellaneous Control 5]
|
| Issue Bad CRC5 in SOF After FIFO Underrun: | Enabled
|
| Lengthen PreSOF Time: | Enabled
|
| Issue Nonzero Bad CRC Code on FIFO Underrun: | Non zero CRC
|
| | |
|
| [Miscellaneous Control 6]
|
| EHCI Supports PME Assertion in D3 Cold State: | Not Supported
|
| UHCI Supports PME Assertion in D3 Cold State: | Not Supported
|
| | |
|
| [Miscellaneous Control 7]
|
| Use External 60 MHz Clock: | Disabled
|
| | |
|
| [USB Release Number]
|
| USB Release Number: | 1.0
|
| | |
|
| [USB Legacy Support]
|
| UHCI v1.1 Compliant: | 2000
|
| |
|
| [General Information]
|
| Drive Controller: | Serial ATA 6Gb/s @ 3Gb/s
|
| Host Controller: | Primary IDE Channel
|
| Drive Model: | PNY CS900 120GB SSD
|
| Drive Firmware Revision: | CS900615
|
| Drive Serial Number: | PNY22442211040101A5D
|
| World Wide Name: | 5F8DB4C224401A5D
|
| Drive Capacity: | 114,473 MBytes (120 GB)
|
| Drive Capacity [MB]: | 114473
|
| Media Rotation Rate: | SSD Drive (Non-rotating)
|
| Nominal Form Factor: | 2.5"
|
| ATA Major Version Supported: | ATA/ATAPI-5, ATA/ATAPI-6, ATA/ATAPI-7, ATA8-ACS, ACS-2, ACS-3, ACS-4
|
| ATA Transport Version Supported: | SATA 3.2
|
| | |
|
| [Drive Geometry]
|
| Number of Cylinders: | 16383
|
| Number of Heads: | 16
|
| Sectors Per Track: | 63
|
| Number of Sectors: | 16514064
|
| Total 32-bit LBA Sectors: | 234441648
|
| Total 48-bit LBA Sectors: | 234441648
|
| Logical Sector Size: | 512 Bytes
|
| Cache Buffer Size: | N/A
|
| | |
|
| [Transfer Modes]
|
| Sectors Per Interrupt: | Total: 16, Active: 16
|
| Max. PIO Transfer Mode: | 4
|
| Multiword DMA Mode: | Total: 2, Active: -
|
| Singleword DMA Mode: | Total: -, Active: -
|
| Ultra-DMA Mode: | Total: 6 (ATA-133), Active: 4 (Ultra-DMA/66)
|
| Max. Multiword DMA Transfer Rate: | 16.7 MBytes/s
|
| Max. PIO with IORDY Transfer Rate: | 16.7 MBytes/s
|
| Max. PIO w/o IORDY Transfer Rate: | 16.7 MBytes/s
|
| Native Command Queuing: | Supported, Max. Depth: 32
|
| TRIM Command: | Supported (Indeterminate Read After TRIM)
|
| | |
|
| [Device flags]
|
| Fixed Drive: | Present
|
| Removable Drive: | Not Present
|
| Magnetic Storage: | Present
|
| LBA Mode: | Supported
|
| DMA Mode: | Supported
|
| IORDY: | Supported
|
| IORDY Disableable: | Supported
|
| | |
|
| [Features]
|
| Write Cache: | Present, Active
|
| S.M.A.R.T. Feature: | Present, Active
|
| Security Feature: | Present, Inactive
|
| Removable Media Feature: | Not Present, Disabled
|
| Power Management: | Present, Active
|
| Advanced Power Management: | Not Present, Inactive
|
| Packet Interface: | Not Present, Disabled
|
| Look-Ahead Buffer: | Present, Active
|
| Host Protected Area: | Present, Enabled
|
| Power-Up In Standby: | Not Supported, Inactive
|
| Automatic Acoustic Management: | Not Supported, Inactive
|
| 48-bit LBA: | Supported, Active
|
| Host-Initiated Link Power Management (HIPM): | Not Supported
|
| Device-Initiated Link Power Management (DIPM): | Supported, Disabled
|
| In-Order Data Delivery: | Not Supported
|
| Hardware Feature Control: | Not Supported
|
| Software Settings Preservation: | Supported, Enabled
|
| NCQ Autosense: | Not Supported
|
| Link Power State Device Sleep: | Not Supported
|
| Hybrid Information Feature: | Not Supported
|
| Rebuild Assist: | Not Supported
|
| Power Disable: | Not Supported
|
| All Write Cache Non-Volatile: | Not Supported
|
| Extended Number of User Addressable Sectors: | Not Supported
|
| CFast Specification: | Not Supported
|
| NCQ Priority Information: | Not Supported
|
| Host Automatic Partial to Slumber Transitions: | Not Supported
|
| Device Automatic Partial to Slumber Transitions: | Not Supported
|
| NCQ Streaming: | Not Supported
|
| NCQ Queue Management Command: | Not Supported
|
| DevSleep to Reduced Power State: | Not Supported
|
| Out Of Band Management Interface: | Not Supported
|
| Extended Power Conditions Feature: | Not Supported
|
| Sense Data Reporting Feature: | Not Supported
|
| Free-Fall Control Feature: | Not Supported
|
| Write-Read-Verify Feature: | Not Supported
|
| | |
|
| [Security]
|
| Security Feature: | Supported
|
| Security Status: | Disabled
|
| Security Locked: | Disabled
|
| Security Frozen: | Enabled
|
| Enhanced Security Erase: | Supported
|
| Sanitize Feature: | Not Supported
|
| Sanitize Device - Crypto Scramble: | Not Supported
|
| Sanitize Device - Overwrite: | Not Supported
|
| Sanitize Device - Block Erase: | Not Supported
|
| Sanitize Device - Antifreeze Lock: | Not Supported
|
| Device Encrypts All User Data: | Not Supported
|
| Trusted Computing: | Not Supported
|
| | |
|
| [Self-Monitoring, Analysis and Reporting Technology (S.M.A.R.T.)]
|
| [01] Raw Read Error Rate: | 100/50, Worst: 100
|
| [09] Power-on Hours/Cycle Count: | 100/Always OK, Worst: 100 (3 hours)
|
| [0C] Power Cycle Count: | 100/Always OK, Worst: 100 (Data = 31,0)
|
| [A8] SATA PHY Error Count: | 100/Always OK, Worst: 100
|
| [AA] Available Reserved Space/Block Count: | 100/Always OK, Worst: 100 (Data = 47,0)
|
| [AD] Wear Leveling Count/Erase Count: | 100/Always OK, Worst: 100 (Data = 1,0)
|
| [C0] Unsafe Shutdown Count: | 100/Always OK, Worst: 100 (Data = 18,0)
|
| [C2] Temperature: | 67/Always OK, Worst: 67 (33.0 °C)
|
| [DA] Number of CRC Errors: | 100/50, Worst: 100
|
| [E7] SSD Life Left: | 100/Always OK, Worst: 100 (Data = 100,0)
|
| [F1] Total Host Writes: | 100/Always OK, Worst: 100 (Data = 12,0)
|
| | |
|
| Drive Remaining Life | 100%
|
| | |
|
| [Device Statistics]
|
| Lifetime Power-On Resets: | 31
|
| Power-on Hours: | 3
|
| Logical Sectors Written: | 25955236
|
| Logical Sectors Read: | 22103569
|
| | |
|
| Number of Reported Uncorrectable Errors: | 0
|
| | |
|
| Current Temperature: | 33 °C
|
| Lifetime Temperature: | 33 - 33 °C
|
| | |
|
| Number of Hardware Resets: | 25
|
| Number of Interface CRC Errors: | 0
|
| | |
|
| Used Endurance Indicator: | 0%
|