Re: GLX Player the only XT player ? Check Mod Master...

Posted on 2019-05-29, 18:33

by

by reenigne

in Marvin \ Sound

in Marvin \ Sound

When it comes to 808x optimization, the smaller code is almost always faster -- the bottleneck for just about everything is taking 4 cycles just to read a byte of memory (on 8086, 4 cycles to read a word of memory). My favourite rule of thumb to get a rough idea of whether a code change will …

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Re: UniPCemu cycle accurate 8088 implementation

Posted on 2019-05-19, 13:49

by

by reenigne

in PC Emulation

in PC Emulation

Edit: Looking a bit further, it seems all those timings concerning " _accessNumber = " are the timings that are probably missing from UniPCemu(except perhaps the CS/IP-related timings, which don't seem to match at all, perhaps because it's based on one of the earlier replies in this thread instead …

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Re: UniPCemu cycle accurate 8088 implementation

Posted on 2019-05-18, 17:55

by

by reenigne

in PC Emulation

in PC Emulation

superfury wrote: Is HLT even used in 8088MPH? Yes, in the Kefrens bars effect. Also in the loader, but it's not time-critical there.

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Re: GCC for 8088/8086

Posted on 2019-04-02, 06:14

by

by reenigne

in Release Announcements

in Release Announcements

Thanks for necroing :) So I got aware of this GCC. Great thing! And the last post indicates it even supports near/far pointers. I ask because I want to modify the driver for Headland HTK340 chipset I wrote in the mid-1990s, and maybe extend its support to the similar HT12 286 chipset. Could I use …

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Re: GCC for 8088/8086

Posted on 2019-04-01, 23:25

by

by reenigne

in Release Announcements

in Release Announcements

Hey reengine, I'm a huge fan of yours and am doing off and on development for Tandy 1000 specifically. I just got your GNU C++ compiler working on CodeBench and am trying to create a hello world program. Whenever I call printf it hangs using DOSBox. I can do other basic things such as malloc, …

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Re: DRAW CALL debugging.

Posted on 2019-02-15, 08:39

by

by reenigne

in DOSBox Development

in DOSBox Development

I'm not sure where you got the idea that red, green and blue are on separate pages in Mode X - I've never heard of a video mode where memory is organised like that! Most VGA games use 256 colours with one byte per pixel and a palette. The separate pages in Mode X correspond to the low two bits of …

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Re: Trying to add Amstrad PC1512 special video mode.

Posted on 2019-02-12, 22:16

by

by reenigne

in DOSBox Development

in DOSBox Development

I'm intrigued by this "Dragonfly" game. Who made it? I assume (from the file date) it was produced in 1994? It's older than that - I changed the file date at some point. I don't have any more information about it I'm afraid. I think it came from a friend but I don't remember which one and I'm not …

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Re: PC UART sending/receiving timing?

Posted on 2019-01-01, 08:45

by

by reenigne

in PC Emulation

in PC Emulation

It depends on the device at the other end of the serial connection, but in general yes - UARTs can send and receive simultaneously (this is what "full duplex" means).

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-26, 12:34

by

by reenigne

in PC Emulation

in PC Emulation

superfury wrote: So: - SS:SP = 0060:0000 - CS:IP = 0060:0100 - 0060:0000 = 00FF - 0060:0002 = 0060 - 0060:00FF = terminate once reached. - DS=ES= […] Show full quote So: - SS:SP = 0060:0000 - CS:IP = 0060:0100 - 0060:0000 = 00FF - 0060:0002 = 0060 - 0060:00FF = terminate once reached. - DS=ES=0060 …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-26, 09:01

by

by reenigne

in PC Emulation

in PC Emulation

So, CLI HLT on 60:FF? Where's the executable loaded? And the initial stack SS:SP? The executable will be loaded at 0060:0100 with an initial SS:SP of 0060:0000. It doesn't matter what instruction is at 0060:00FF, that's just the CS:IP that emulator looks for to know when to stop. It's been pointed …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-24, 16:44

by

by reenigne

in PC Emulation

in PC Emulation

I made an executable version of XTCE: http://www.reenigne.org/misc/xtce.zip . Doesn't need any DLLs except for the VC++ runtime which you can get at https://www.microsoft.com/en-us/download/details.aspx?id=52685 if it complains about vcruntime140.dll being missing. Give it a .com file on the command …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-24, 08:45

by

by reenigne

in PC Emulation

in PC Emulation

@reenigne: If your EU cycle counts for those instructions(the totals, excluding specific timings in between(e.g. part before and part after memory access only being applied after a memory transaction(e.g. mov al,[bx]), then those should be working(theoretically). The CRTC should be functioning …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-23, 22:46

by

by reenigne

in PC Emulation

in PC Emulation

Also, in UniPCemu's DMA emulation, only SI, S0, S1, S2, S3 and S4, where S4 can become SI(or even further into S0), depending on a running block transfer(depending on if the bus is released). https://bitbucket.org/superfury/unipcemu/src/1c0a992eef3171382903e4a32d20df3404d7e5eb/UniPCemu/hardware/dma …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-22, 16:28

by

by reenigne

in PC Emulation

in PC Emulation

How exactly do I determine when to return how many clces for the DRAM refresh wait state? It's complicated! Here are some sniffer logs I made that show the possible timings: DMA states: sDREQ sHRQ, sHoldWait sAEN s0 s1 s2 s3 sWait s4 sDelayedT1 sDelayedT2 sDelayedT3 20FFF .p... 00F16 FF 00 FC …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-22, 16:02

by

by reenigne

in PC Emulation

in PC Emulation

So far it appears to run fine, except that the credits have no sound but that's because the emulation of the PIT and the PC speaker leaves a lot to be desired, so it's on my list to be eventually either rewritten or ported from DOSBox where I heard PIT mode 1 (which I presume the credits use) works …

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Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Posted on 2018-11-22, 15:11

by

by reenigne

in PC Emulation

in PC Emulation

Wow, very cool! Does 8088 MPH run correctly now? I might need to get a move on with the next (even more sensitive) testcase! As for the original question about multiply/divide timings - there was a thread here a while ago (https://www.vogons.org/viewtopic.php?f=9&t=62817) where I pointed superfury …

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Re: x86 INS/OUTS vs DMA method?

Posted on 2018-10-24, 07:18

by

by reenigne

in PC Emulation

in PC Emulation

That's not what I mean. Does the CPU use an internal register to store the data for/from RAM, or does it exploit the data bus retaining the value by performing a read/write at the same time like DMA does? So write to memory at the same clocks while the hardware supplies tje data lines the very same …

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Re: x86 INS/OUTS vs DMA method?

Posted on 2018-10-24, 07:06

by

by reenigne

in PC Emulation

in PC Emulation

The way to think about it is that DMAs transfer between memory and some other device, without involving the CPU (other than blocking it from the bus for the duration of the transfer). Port IOs (IN(S)/OUT(S)) transfer between the CPU and some other device, without involving memory. So they're totally …

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Re: 8086 multiplication algorithm?

Posted on 2018-10-09, 11:51

by

by reenigne

in PC Emulation

in PC Emulation

superfury wrote: There are still 100-ish cycles missing somewhere(assuming 8088MPH reports cycle difference and not PIT counter difference?) It reports PIT counter difference 😀

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Re: 8086 multiplication algorithm?

Posted on 2018-10-08, 11:47

by

by reenigne

in PC Emulation

in PC Emulation

OK. With the latest improvements(missing REP cycles and instruction startup cycle(1 cycle at the beginning of your handler), 8088 MPH now reports 1563 metric cycles. Still something is missing? Edit: I do remember some of your instructions(like HLT) adding some cycles based on T-state and REP …

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