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Re: x86 LOCK signal vs DMA?

Just implemented the lock signal to happen from the first memory I/O until the instruction finishes(e.g. during it's final cycles after the memory accesses, until the next instruction is going to start at the next cycle(the BIU is already finished doing it's work for the currently executing …

x86 page fault priority?

When an entry isn't found in the TLB and to be loaded from memory, what is the order of page fault checks that are executed? There's checking on the PDE's Present bit, the PTE's present bit and the rights(privilege and read/write). It currently first checks the PDE's present bit, then the PTE's …

x86 IDT access rights size bit(bit 3) effect?

What does the IDT's Access Rights' Size-bit control(bit 3 of the Access Rights for Interrupt and Trap gates)? All I can find are descriptions saying 16-bit for 0 and 32-bit for 1. But there's no explanation I can find ANYWHERE what this bitness applies to? It can't be stack size, as that's done by …

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