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Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-03-01, 11:17

This is what BSOD I'm getting now: 1057-Windows NT BSOD after fixing REP faults..jpg Edit: Slightly improved the logging of the Page Faults: dolog("pagefaults","#PF on instruction osize:%u,asize:%u 0F:%u OP:%02X R/M:%02X at %08X on VA %08X code %04X",CPU_Operand_size[activeCPU],CPU_Address_size[ …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-03-01, 10:15

Whoops! That's because the interrupt is incorrectly being handled! The interrrupt pushes it's data on the stack and jumps to the interrupt handler(the EFLAGS,CS,EIP being pushed). But once it's starting the first instruction from said handler(initializing instruction phase), the REP bugfix (that's …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-03-01, 03:16

Well, it seems to cause a page fault(null pointer dereference) directly after doing some IDT modifications(80486 CMPXCHG faulting on the 80386 emulation), then setting some more vectors, then setting the Trap flag(by means of an POPF instruction), whose handler(the Trap fault handler) page faults(LA …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-02-28, 22:32

Interestingly enough, I see only one fault being raised by the CPU before triggering the NULL pointer dereference which causes the BSOD: an INT1 exception is being triggered? That doesn't seem to be supposed to happen? Edit: It seems to happen because the trap flag is set? The last instruction was a …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-02-27, 19:32

So Windows NT is trying to RETF to the location in the second DWORD stored in IDT vector 1(single-step interrupt)! That's already setup at the start of the log, which is even weirder! So the code is using the IDT as something that's supposed to be an instruction or data address' location, and ret- …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-02-27, 18:40

I can trace the invalid return address which tries to use EDX as a pointer(RETF) to: 0008:801bae46 FF 73 0C push dword ds:[ebx+0c] RealRAM(p):0015ae53=e8(?); RAM(p):001bae53=e8(?); Physical(p):001bae53=e8(?); Paged(p):801bae53=e8(?); Normal(p):801bae53=e8(?); RealRAM(p):0015ae54=10(); RAM(p): …

Re: x86 TLB set vs way?

Posted on 2019-02-27, 16:33

Just reversed the whole set vs way logic in UniPCemu(only TLB changes with their calls from the Paging emulation). Now it's Set-associative instead of Way-associative(which it was until now, from TR6/7(also in execution, especially noticeable when using TR6&7, since it used the associative memory in …

Re: x86 TLB set vs way?

Posted on 2019-02-27, 15:07

So, if reading it again, I've understood it correctly: - A lookup/store has a set, determined by the low 3-bits of LA(bits 12-14). - The associative entry(four of them) return a result(an entry with an array index(stored in the REP field of the TR6/TR7 on lookups/stored) of a set, which is a list …

Re: x86 TLB set vs way?

Posted on 2019-02-27, 14:28

Looking at the 80386 and i486 programmer's reference manual's description of the TR6&TR7 registers reveals something interesting: they say the same(minus the P-bit for TLB writes). So it's actually 4 ways(sets incorrectly labeled for 386 instead of ways) with 8 sets for both. Ways are selected by …

Re: x86 TLB set vs way?

Posted on 2019-02-27, 12:51

Just reread that section. So the 'set' is essentially a block of four entries(that contain four addresses), selected by the low 3-bits of the tag's address. Within those four entries, it uses one of them to allocate/read/write/use/free a (new) entry. So it's the same as the 8 entry four ways with a …

Re: x86 TLB set vs way?

Posted on 2019-02-27, 11:08

What I mean is(as UniPCemu implements it): - It uses a set, based on the lower 2-bits of the logical frame(bits 12-13). Currently it's still bits 29-30. - Said set has 8 TLB entries. Those are dynamically allocated using a simple linked list for speed(allocation and deallocation is done using two …

x86 TLB set vs way?

Posted on 2019-02-27, 08:10

What is the difference between a set and a way? The i486 microprocessor programmer's reference manual says the following(page 10-7): - 4 ways, 7 sets for each way. - bits 12-14 of LA select the set? Isn't the "way"/"set" selected by those bits? (2-bit on 80386) What's the difference between a way …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-02-26, 00:46

With the latest bugfixes, I now immediately see it #PF on LA 0 using DS(23h):0 as a pointer after the #UD(using opcode 01h, ADD), which NT doesn't like... Still typical, fixing one bug, another one pops up(until none are left)! It happens at 0008:80168E00, opcodes 011A(ADD DWORD [EDX],EBX). debugger …

Re: Behaviour of reg32 with SMSW/SLDT/STR?

Posted on 2019-02-25, 15:24

Hmmmm.... Bochs seems to agree on SMSW. But it does support 32-bit registers on STR and SLDT? if (i->modC0()) { 303 if (i->os32L()) { 304 BX_WRITE_32BIT_REGZ(i->dst(), val16); 305 } 306 else { 307 BX_WRITE_16BIT_REG(i->dst(), val16); 308 } 309 } 310 else { 311 bx_address eaddr = BX_CPU_CALL_METHODR …

Behaviour of reg32 with SMSW/SLDT/STR?

Posted on 2019-02-25, 14:42

What is the resulting value of the register when using e.g. EAX with SMSW, SLDT and STR on a 80386/80486? It seems "SMSW EAX" is used with some MS-DOS extenders, but that might not be working on a 80386? What about STR and SLDT? https://github.com/corkami/docs/blob/master/x86/x86.md http://board. …

Re: UniPCemu Windows 95/NT progress and issues

Posted on 2019-02-23, 23:46

With the latest improvements, Windows NT now generates a STOP 0000007B inaccessabls boot device? Anyone? Edit: Interestingly, I see no non-#PF faults anymore. Only lots of page faults(only whatt seems to be stuff like copying memory blocks usimg MOVSD mostly between 000XXXXX and 800XXXXX)? Anyone …

x86 LMSW from Virtual 8086 mode is allowed?

Posted on 2019-02-23, 12:39

Looking at the 80386 instruction set again, CR0 can't be modified from Virtual 8086 mode(throwing #GP(0)): https://pdos.csail.mit.edu/6.828/2005/readings/i386/MOVRS.htm But looking at LMSW reveals something odd: https://pdos.csail.mit.edu/6.828/2005/readings/i386/LMSW.htm The Virtual 8086 column …

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