VOGONS

Common searches


Search results

Display options

Re: UniPCemu 8088 cycle accuracy

I've just added a neat little feature to UniPCemu's softdebugger: software triggered debugger logging. So software can instruct the debugger to start logging at a specified point in execution and instruct it to stop logging when needed. The basic protocol to set it up is done using a normal …

Re: UniPCemu 8088 cycle accuracy

Just implemented an extra timer on the BIU emulation of the 808x: - When T3 is ticked (proceeding onto T4), it will set a flag if the prefetch isn't empty. - When T1 arrives to tick and either said flag is set, or no request is made, an additional check is made before checking the requests from the …

Re: UniPCemu 8088 cycle accuracy

Just implemented an extra timer on the BIU emulation of the 808x: - When T3 is ticked (proceeding onto T4), it will set a flag if the prefetch isn't empty. - When T1 arrives to tick and either said flag is set, or no request is made, an additional check is made before checking the requests from the …

Re: UniPCemu 8088 cycle accuracy

I've been thinking... Is there a difference in bus stalls? As in, is a BIU stall and BUS stall the same or are they different in some way internally to the BIU? Edit: As a side note, just implemented DRAM refresh setup for the DMA and PIT (PIT channel 1 and DMA channel 0 only, others unaffected) …

Re: UniPCemu 8088 cycle accuracy

I've been thinking... Is there a difference in bus stalls? As in, is a BIU stall and BUS stall the same or are they different in some way internally to the BIU? Edit: As a side note, just implemented DRAM refresh setup for the DMA and PIT (PIT channel 1 and DMA channel 0 only, others unaffected) …

Re: UniPCemu 8088 cycle accuracy

Just improved the instruction logging to: - Log executed instruction and debugging information once the execution finishes. - Log instruction address once the execution stars until the execution finishes (so the entire execution phase is visible). So a 2-cycle EU far JMP absolute address instruction …

Re: UniPCemu 8088 cycle accuracy

And the full cycle log of the 8088 metric batch using the BIOS COM ROM: Filename debugger 8088 cycle count extracted 20230802_1031.7z File size 16.25 KiB Downloads 30 downloads File comment 8088 metric cycle batch Edit: Simplified with the extra clutter disabled in UniPCemu (advanced logging and …

Re: UniPCemu 8088 cycle accuracy

Managed to fix an issue with the debugger not logging T-states when requestsed to do so with the common log format log settings. Although the cycle count seems weird for the first JMP instruction in that case (only 1 transfer for the entire instruction) in cycle-accurate logging of the BIOS COM ROM …

Re: UniPCemu 8088 cycle accuracy

Just managed to compile your 8088MPH executable with the segment prefixes (CS: etc.) moved inside the brackets (the nasm compiler was complaining about them being "error: invalid combination of opcode and operands"). Now that I have the ROM, I should be able to run it using the BIOS ROM (with of …

Re: UniPCemu 8088 cycle accuracy

What metric cycle count does it expect? I can't find it in previous posts. It's an adjusted delta of PIT ticks. Timer #0 is set at the start and read at the end of the routine. the difference is your 'score'. then an adjustment is made I don't fully understand, but ends up subtracting ~100ish ticks …

Re: UniPCemu 8088 cycle accuracy

Any idea where I can find how many cycles each CPU opcode is supposed to take? You can use XTCE-trace ( https://www.reenigne.org/software/xtce_trace.zip ) or MartyPC or the ISA bus sniffer on XTServer. I think the timings from these should almost all be the same as those from the previous version …

Re: UniPCemu 8088 cycle accuracy

Trixter wrote the speed test, not me. But I believe it just runs a particular block of code (containing many different types of instructions) and counts how many PIT cycles it took to execute. The correct value should be 1678, so a report of 1720 means that the emulated CPU is slow - taking too …

Re: UniPCemu 8088 cycle accuracy

I've been thinking... If 8088 MPH reports 1720 cycles (atm), what does that mean? Does that mean that the instructions executed took too many(thus absolute cycle count of all instructions in the test combined, a straight out read difference in PIT cycles, higher count meaning more cycles/instruction …

Re: UniPCemu 8088 cycle accuracy

Just tried Area 5150 again, and the results are.... Interesting... https://www.dropbox.com/s/hr9nxq9zjefuifa/UniPCemu%20Area5150%202023-07-31%2022-31-40.7z?dl=0 The output of the cycle-accurate parts is less stable in retracing sometimes, but a bit more stable horizontally now? Still lots of …

Re: UniPCemu 8088 cycle accuracy

GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)). No, the difference between PC and XT with DMA is only in …

Re: UniPCemu 8088 cycle accuracy

GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)). The motherboard might have waitstates for bus(I/O, 1 on PC …

Re: UniPCemu 8088 cycle accuracy

Why would prefixes taking less EU and BIU cycles for prefixes (proper 2 (1 EU PIQ and 1 prefix parsing) instead of 3(1 EU PIQ and 1 prefix parsing)) return a higher metric cycle in 8088 MPH? Shouldn't it run those instructions faster (less cycles), lowering it instead?

Re: UniPCemu 8088 cycle accuracy

8088 MPH now report 1662 (1%) now! :D Btw, I'm testing with the Final 8088 MPH version. Edit: The 16-color noise moved again, to 1 clock before the clock before the "1" starts, as well as the clock before the clock where the 2 of "256 COLORS" starts rendering (as well as the 1st scanline, which …

Re: UniPCemu 8088 cycle accuracy

Thinking about it, the same now also applies to instructions with only an imm (no r/m). Is that correct behaviour as well? (Like opcodes, 04/05, 14h,15h (until 3Ch/3Dh), as well as A0-A3 (mov moffs(the immediate),al/ax and reversed direction) and B0-BF(mov reg,imm)) Edit: Leaving the 286+ CPU issue …

Page 14 of 275