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Re: Memory for protected mode DOS games

in DOS
Thinking about it, the 80386 might only be needed for the CD-ROM interface? Otherwise, a 80286/80186(NEC V20/30) should work as well. Well, I know UniPCemu still has little CPU bugs, but I can't seem to find them(other than a few 80186(EPC) testsuites failing the MUL and two other tests, for some …

Re: Memory for protected mode DOS games

in DOS
Does the Day of The Tentacle run on a 8086 or 80186 CPU? If it doesn't, it needs a 80286 to work(since it won't run 80286+ instructions on those CPUs). The 80286 only adds new instructions for entering and managing protected mode, so if it doesn't use Protected Mode, it should run on a 8086 or 80186 …

Re: XT-IDE BIOS AT Problems with UniPCemu?

After a bit of tinkering with the hard disk commands(in particular, fixing the Set multiple mode command and drive parameters that are based on it). It now properly starts to boot MS-DOS, ending up reading IO.SYS(3 sectors afaik), then crashing with an #UD(which loops infinitely to the faulting …

Re: XT-IDE BIOS AT Problems with UniPCemu?

After looking at the BIOS i/o, it doesn't seem to ever set the register A of the CMOS to any value other than 0? That effectively disables all interrupts(since it doesn't count)? I've curcumvented this by loading a value of (2<<4)|6 when initializing the RAM(when not saved already). Thus it's …

Compaq Deskpro 386 EISA secondary PIT?

When I look at the bochs' ports.lst, I see the following entries: 0044 r/w PIT counter 3 (PS/2, EISA) used as fail-safe timer. generates an NMI on time out. for user generated NMI see at 0462. 0047 w PIT control word register counter 3 (PS/2, EISA) bit 7-6 = 00 counter 3 select = 01 reserved = 10 …

Re: XT-IDE BIOS AT Problems with UniPCemu?

I've managed to get the XT-IDE BIOS AT version to properly load the boot sectory, but after that it looks like some rogue reads XT(correctly booting): CHS-based addressing when bit 30 is set(starts with A most of the time). XT: A00000001=0 A10000001=3F A80000031=228 A90000012=248 A90000013=249 …

Re: XT-IDE BIOS AT Problems with UniPCemu?

It now properly flashes the BIOS(although I still need to manually adjust it to use only the first controller(it's still detecting the CD-ROM drives as harddisks)). Now it ends up at some infinite loop, waiting for an IRQ0 tick count to be set, which doesn't update it seems?

Re: XT-IDE BIOS AT Problems with UniPCemu?

After testing it with the newest data protection handling(SDP commands according to the manual), it crashes, because byte 0xAAA contains 0x55, failing the BIOS checksum? Don't the writes to the EEPROM get written normally(the documentation from Atmel doesn't say anything about it)? The 0xAAA address …

Re: XT-IDE BIOS AT Problems with UniPCemu?

I've found a few little problems with the EEPROM emulation I am using (Atmel AT28C64B 64K flash ROM emulation requiring a ROM of at least 5462 bytes to make the SDP commands work, otherwise it acts like a simple ROM instead of a flash ROM(effectively never being able to finish the SDP command, …

Re: XT-IDE BIOS AT Problems with UniPCemu?

Just found a little problem with the ATA/ATAPI status register: entering a new command phase(e.g. no command is running, controller is waiting for a new command to be specified without any pending error handling) will now cause: - Busy bit to become 0. - Drive ready bit becoming zero after drive …

Re: XT-IDE BIOS AT Problems with UniPCemu?

One strange thing is currently occurring: it does detect the secondary controller(at base ports 0x170/0x376) which are emulated ATAPI-4 CD-ROM drives, but doesn't detect the primary controller(at 0x1F0/0x3F6) which handles the hard drives. It's giving me Base(cmd block) address 0x170 and Control …

Re: XT-IDE BIOS AT Problems with UniPCemu?

Yes, I'm using the latest official AT version(https://storage.googleapis.com/google-code-archive-downloads/v2/code.google.com/xtideuniversalbios/XTIDE_Universal_BIOS_v2.0.0_beta3.zip, file ide_at.bin. It has a copy of the XT configuration(loaded from the XT ROM(which works), then flashed the AT ROM( …

Re: x86 task switching vs double faults?

I already have that implemented, with the faults after the task switch(loaded incoming TSS) continuing to compare. So the fault before the task was switched is taken as the first(left column), while any faults after the incoming TSS is loaded into the registers(loading descriptors and TSS checks) …

x86 task switching vs double faults?

When the x86 CPU switches tasks because of a fault(e.g. general protection fault pointing to a task gate), switches to the general protection fault task(incoming task) and tries to push the error code, which fails due to an stack fault. Will the stack fault become a double fault? It probably will, …

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