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Compaq Deskpro 386 keeps complaining about CMOS?

Posted on 2017-11-15, 19:45

I have the CMOS fully emulated(with RTC clock synchronized with actual system time difference(in nanoseconds) instead of in-emulation clock, although interrupts are synchronized with the emulator CPU clocking). It emulates 128 bytes of CMOS RAM at 0x70/0x71. But the Deskpro 386 keeps complaining …

Re: test386.asm CPU tester

Posted on 2017-11-15, 19:06

Doesn't the documentation all say that 8-bit ROL/ROR mask with 0x1F, then modulo 8(which is the same as &0x7, as is done in my emulator for optimized performance)? Thus (8&0x1F)%8=(8&0x1F)&7=0, thus nothing is shifted/rotated? Only with RCL/RCR, the modulo is 9 instead, thus actually shifting with " …

Re: UniPCemu emulator releases

Posted on 2017-11-15, 13:34

My latest UniPCemu release: UniPCemu_20171115_1322.zip Android release: https://www.dropbox.com/s/bnirqhuot06jr8k/UniPCemu-20171115_1322.apk?dl=0 Changelog: - Added support for 32-bit single diagnostics ROM and XT/AT/XT286 diagnostics ROMs to be loaded automatically. - Extended log support for time …

Re: MS-DOS disk image CHS compatibility?

Posted on 2017-11-15, 01:04

I've made the disk CHS partitioning autodetect a bit more configurable: - Old sfdimg files will use a compatibility CHS layout(the defined ifdef part in my code). - New sfdimg files will use the new improved autodetect CHS layout(based on rules described earlier, this method is done by a disk image …

Re: test386.asm CPU tester

Posted on 2017-11-14, 15:55

So, let's assume the testsuite(without cpu specific part) validates OK. Then why does Windows 95 setup still crash loading(no output) due to Bound Exception due to ModR/M offset overflow or invalid bounds in memory? Any known untested opcodes in the testsuite?

Re: test386.asm CPU tester

Posted on 2017-11-14, 15:15

Just tried running the Windows 95a boot disk again. With the latest shift/rotate fixes, the boot image palette scrolling works without problems now! (instead of just inserting white at the right side, scrolling in white) It now properly rotates and adjusts the palette! :D It's still slow for some …

Re: test386.asm CPU tester

Posted on 2017-11-14, 13:58

I've applied all your comments to the code, except RCL, which only gives correct (errorless) results when it the count around like the other instruction(&0x1F instead of %33). When it uses %33(for 32-bit rotate), the results will become entirely wrong some edge cases. When reverted to &0x1F, ALL …

Re: test386.asm CPU tester

Posted on 2017-11-14, 13:36

I've modified the code to wrap around 33 bits, but after some bugfixes, it seems that the RCL r/m32 instruction doesn't shift enough sometimes? 8-bits: byte op_grp2_8(byte cnt, byte varshift) { //word d, INLINEREGISTER word s, shift, tempCF, msb; INLINEREGISTER byte numcnt, maskcnt, overflow; //word …

Re: test386.asm CPU tester

Posted on 2017-11-14, 05:40

Documentation says mask with 0x1F, even with 32-bit rcl/rcr? rol al,8 will modulo 8 with 8, becoming 0, thus not rotating anything, thus no carry flag modification? Or is it set to bit 0 with 8/16 shifts always? With count(s), do you mean cnt, maskcnt or numcnt in those statements?

Re: test386.asm CPU tester

Posted on 2017-11-13, 17:25

I've adjusted the formulas on the 8-bit and 16-bit variants to match it's (correct) 32-bit counterpart, but the carry flag still fails? All other flags give no errors. The carry flag fails on ROL B/W, ROR B/W and RCR B/W only? porte9.log 8-bit: byte op_grp2_8(byte cnt, byte varshift) { //word d, …

Re: test386.asm CPU tester

Posted on 2017-11-13, 14:38

Adjusting the flags to always be updated after each 1-bit shift(even subshifts of multiple CL or imm8 shifts), gives the following errors: ROLr B/W: carry flag RORr B/W: carry flag RCRr B/W: carry flag Finally, progress! :D So finally, no overflow flag problems anymore:D The only (strange) problem …

Re: test386.asm CPU tester

Posted on 2017-11-13, 12:56

Just tried converting the logic for the single-bit shifts to multi-bit shifts: 8-bit shift/rotate: byte op_grp2_8(byte cnt, byte varshift) { //word d, INLINEREGISTER word s, shift, tempCF, msb; INLINEREGISTER byte numcnt, maskcnt, overflow; //word backup; //if (cnt>0x8) return (oper1b); //NEC V20/ …

Re: test386.asm CPU tester

Posted on 2017-11-13, 05:48

So shifting anything(count!=0) will (re)set the overflow flag according to the old and new sign flags(old xor new sign flag)? XOR of the TOP two bits before AND after? Don't you mean XOR of the top bit(sign bit before xor sign bit after)? Or do you mean: OF = (MSB(oldval) xor SMSB(oldval)) and (MSB( …

Re: test386.asm CPU tester

Posted on 2017-11-11, 23:47

Just looked at IBMulator's code. It seems to do things like Bochs and Dosbox, and with the same results thay should match Carry flag, but it doesn't? Overflow is always affected with maskcnt!=0(and maskcnt==8(byte)/16(byte/word)/24(word) for rol/ror? Does IBMulator's output match real hardware(which …

Re: test386.asm CPU tester

Posted on 2017-11-11, 21:24

Adjusting the code based on the manual(except the src argument, which probably isn't correct?) results in the following log: porte9.log It still errors out, even though it fully matches the documentation? OF and CF are updated accordingly as the documentation says it does(except CF updating within …

Re: test386.asm CPU tester

Posted on 2017-11-10, 23:09

So OF is only affected when maskcnt==1, CF is always set to the last shifted bit(except without numcnt, which leaves it untouched(except with ROL/ROR, which will load even when shifting e.g. 8 or 16, which doesn't shift due to modulo shifting(numcnt==0))? tempCF ← LSB(SRC); DEST ← (DEST / 2) + (CF * …

Re: test386.asm CPU tester

Posted on 2017-11-10, 19:05

So when what count is overflow (re)set? The original(cnt), the masked(maskcnt) or the actual shifts(numcnt)? The setting of the carry bit is already done that way(see code), but still incorrect according to the reference?

Re: test386.asm CPU tester

Posted on 2017-11-10, 14:55

So indeed, the sign extension is remedied by simply and-ing out the high 33/17/9 bits(sign bit and higher). Now those results are as required. I've modified all instructions a bit, but for some odd reason the carry and overflow flag(even with ROLi, which shouldn't happen according to documentation!) …

Re: test386.asm CPU tester

Posted on 2017-11-10, 09:17

One very important question: does the overflow flag depend on the shift count(needing to be 1), shift instruction(1-shift instruction, CL shift instruction or immediate shift instruction(186+)), the shift count(being any 8-bit number depending on the used value in instruction(1-shift), CL or …

Re: test386.asm CPU tester

Posted on 2017-11-10, 01:28

I've just added some 0x7F, 0x7FFF and 0x7FFFFFFF masks to the "(s>>1)" parts (e.g. becoming "((s>>1)&0x7F)"). That was applied to the ROR and RCR instructions. Now the results all match up to the real CPU(all but the flags). :D The only bugs still left are (oddly enough) the carry flag and overflow …

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