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Floppy Disk Controller result phase MSR value?

I currently set RQM(bit 7)=1, Have data for CPU(bit 6)=1 and Busy (bit 5)=0 during the result phase. The controller remains in the result phase while there's result data to be read. Is this correct? So while reading the result bytes (e.g. during the 7 result bytes of a read floppy sector) bits 7 and …

ISA DMA emulation: how to handle TC and DREQ?

At the moment, my emulator keeps checking the DREQ line (raised/lowered by the FDC). My FDC also raises the EOP line when it enters the result or error phase. How should the Terminal Count and different modes of operation be handled? Does the Terminal Count have any effect on transfers? What's the …

MIDI Channel 9(0-based) bank select 0x7F?

I notice that in my emulator, when playing a MIDI file (.MID file) a bank select MSB/LSB pair is sent to my MIDI Synth with a bank number of 0x7F(127). Should the channel respond to this message? Since it's a piano and not a MIDI drumkit on this bank it shouldn't use this bank?

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