Re: Aopen AX59 pro with general instability

Posted on 2020-08-15, 09:31

by

by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

The VRM looks like a good synchronous buck. I would replace 4 output capacitors solid polymers 6.3V or 4V, 10mm diameter, 1500uF most likely. 2 input capacitors with 6.3V, 8mm diameter, 1000uF to 1500uF; also all other 8mm capacitors on this board with these to be safe.

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Re: The World's Fastest 486

Posted on 2020-08-13, 19:53

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I wish I still had my 8433UUD! I sold it off about 20 years ago now lol Anyway, as far as fastest 486 goes, doed overclocking count? One of my mates at tech bought in his overclocked 486 system into class. It was overclocked to 200 MHz! He had to change the crystal on the motherboard from memory. I …

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Re: Upgrading a 386SX - some advice!

Posted on 2020-07-18, 12:29

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

It is also worth to mention that chipsets also have their overclocking limits. Many 386SX chipsets were 20MHz or 25MHz rated. There is no guarantee they will do 33MHz or 40MHz even if everything else is in a great shape.

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Re: Upgrading a 386SX - some advice!

Posted on 2020-07-18, 12:24

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

80ns RAM is generally good up to 33MHz and 70ns up to 50MHz, but it depends. 386SX based mainboards were low end back in the day, so don't expect many good capacitors there. Even if there are no electrolytic ones, I'd suggest to replace some on the +5V rail near the CPU, chipset and RAM slots with …

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Re: Pentium MMX 450MHz

Posted on 2020-06-23, 19:32

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Very interesting! I only came across the non-temporal store when I converted the upscaler of chocolate doom to use the 16 byte wide registers to duplicate bytes and write the finished frame buffer scaled up by integer multiples. It was faster then wr-alloc even though I was writing consecutive …

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Re: Pentium MMX 450MHz

Posted on 2020-06-23, 01:56

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Just for the record, screen shots of K6-2 and K6-3 running on the same mainboard with the same settings. write performance in MB/s K6-2 K6-3 Tillamook L1 MMX 2425.74 2489.26 169.60 L2 MMX 245.39 1248.84 168.95 L3 MMX 245.34 Mem MMX 110.00 144.89 169.21 BTW why write performance is such BS on many …

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Re: Pentium MMX 450MHz

Posted on 2020-06-22, 21:57

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Maybe Tillamook support has something to do with the base BIOS version? FIC VA-503+ as well as PA-2012 and PA-2013 use Award 4.60PG while most other Socket 7 boards run 4.51PG. I have got a batch of Tillamooks from Chinese scrappers. The best one does 450MHz @ 2.3V which is way better than 2.8V.

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Re: Pentium MMX 450MHz

Posted on 2020-06-20, 07:10

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

It won't go any higher in this FIC VA-503+ as the board is unstable at 124MHz. It's also picky about video cards. Had to put a Voodoo 3 instead of a Radeon 7500. I guess that's the board's not optimal layout.

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Re: Pentium MMX 450MHz

Posted on 2020-06-07, 21:24

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

How stable is it running at 450Mhz? The record 533Mhz is said to be done at 3.1V and with air cooling :0 https://hwbot.org/hardware/processors#key=embedded_pentium_mmx_266mhz I wish I had one or two of these CPUs, Maybe its faster than K6 in Half life ! lol Just imagine if Intel made it 180nm and …

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Re: Pentium MMX 450MHz

Posted on 2020-05-26, 21:18

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Are the capacitors good on your boards? I have upgraded mine from those nonames near the CPU socket to Rubycon MBZ 2200uF/6.3V liquids and Fujitsu 560uF/4V polymers. Besides I have modded the socket, so it saves me the trouble of modding every Tillamook that gets in my way. Other CPUs don't care …

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Re: The World's Fastest 486

Posted on 2020-05-03, 04:13

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Many chipsets of early 1990's defaulted to write back cache without a dirty bit in tag SRAM. It allowed for a larger cacheable range, but led to excessive writes because every line in cache was considered dirty. Write through is generally better than write back without a dirty bit.

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Re: Socket 5 Processors and MB Cache

Posted on 2020-04-23, 09:54

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

pentiumspeed wrote on 2020-04-23, 02:00: Even with no cache, what's the impact using SDRAM instead of EDO? It's noticeable. You have to get those early 32Mb SDRAM modules though.

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Re: Pentium MMX 450MHz

Posted on 2020-04-22, 18:11

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I'm actually unable to run the tillamook, I tried it on the following mb without success: Epox MVP3G5, Aopen AX59 PRO (both with Via MVP3) then I tried a Asus SP98AGP-X (sis ss7 chipset) in all of that mb I get black screen. These ASDC# to ASD# and BRDYC# to BRDY# bridges are only for mainboard …

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Re: Socket 5 Processors and MB Cache

Posted on 2020-04-22, 12:24

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

SRAM was still expensive when Socket 5 was in production. Many mainboards had DIP sockets for cache memory and could take up to 2Mb. Later models switched from async SRAM in DIP sockets to pipelined burst SRAM in PQFP chips. The usual configuration was 256Kb soldered to mainboard and additional …

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Re: Pentium MMX 450MHz

Posted on 2020-04-21, 23:55

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

By the way, Speedsys shows that the L3 cache bandwidth on this motherboard is about 180 MB/s while main memory bandwidth is 160 MB/s so the difference is not that impressive. Reading from mainboard cache is 528MB/s, from memory is 337MB/s. Somewhat slower on Tillamook, but the same order of …

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Re: Pentium MMX 450MHz

Posted on 2020-04-21, 21:12

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I really don't have a lot of faith in Speedsys' benchmarks. It's really just a number that doesn't really correlate to the speed of the system as a whole. That said, it's still super impressive. I'd love to see how it runs early Win98 titles. Also what are you doing to keep the chip cool? At 2.8V I …

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Re: Pentium MMX 450MHz

Posted on 2020-04-21, 14:25

by

by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I run my K6-III+ with the motherboard cache disabled. It's actually slightly faster in DOS Quake that way, and I benchmarked it many times to make sure it's not a measurement error. Other games are slightly slower but the difference is about the same as the difference between K6-III+ and K6-II+ at …

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Re: Pentium MMX 450MHz

Posted on 2020-04-21, 14:22

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Just for the record, screen shots of K6-2 and K6-3 running on the same mainboard with the same settings. https://i.imgur.com/1ZAraqC.png Cache Level 1 1677.63 MB/s read 1643.74 MB/s write 1645.15 MB/s move 1655.50 MB/s average Cache Level 2 528.49 MB/s read 245.38 MB/s write 245.38 MB/s move 339.75 …

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Re: Pentium MMX 450MHz

Posted on 2020-04-21, 13:49

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

There are BRDY# and ADS# signals on the P5 system bus which indicate beginning of every read/write bus transaction. These are shadowed by BRDYC# and ADSC# signals intended for mainboard cache subsystem because the system bus in dual processor mode is heavily loaded. Intel removed support for dual …

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Re: Pentium MMX 450MHz

Posted on 2020-04-20, 23:38

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by ph4nt0m

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I have fixed the cache issue :) There are BRDY# and ADS# signals on the P5 system bus which indicate beginning of every read/write bus transaction. These are shadowed by BRDYC# and ADSC# signals intended for mainboard cache subsystem because the system bus in dual processor mode is heavily loaded. …

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