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Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-27, 12:09

So basically RNI_END would be where UniPCemu stops dumping the instruction address (where EU cycles ended and fetching the next instruction starts)? I don't know what "dumping the instruction address" refers to, sorry. And the second cycle is the start of the MOV AL,12 EU's fetching of the …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-26, 22:55

Also, your log is kind of confusing. Where do instructions start fetching, I can't see where they start? In many cases, instructions are already being fetched during the previous instruction. If you look in the last column, "RNI" indicates the last cycle of microcode execution for an instruction, …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-26, 16:41

And PF/EU->idle? I'm not sure, actually, but I model it as one cycle. - PF/EU to idle: 3 cycles This is likely going to be too slow I've published a blog article on the 8088MPH CPU test. Included is a cycle-perfect trace of the CPU test execution including a column that shows my BIU state …

Re: MartyPC

Posted on 2023-08-26, 15:01

1) Is support for protected floppy disks planned? That's probably the one thing that would eliminate the need for a real old PC (or PCE emulator) to play old games in the most authentic way. I mean *.TD0 and *.TC, maybe *.IMD as well. Yes, it's something I'd like to add. 5) Some booter games do not …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-26, 14:48

I've just managed to get the new BIU states implemented (3 cycles to switch between EU, PIQ and idle states in parallel to normal transfers), as mentioned in your article on the BIU's 3-modes machine. It's now taking 3 parallel cycles (executed in parallel to the normal T-states) for every mode …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-20, 23:37

Hi superfury, are you familiar with Tom Harte's CPU test suites? https://github.com/TomHarte/ProcessorTests/ they are a set of JSON files with initial and ending state information for single instructions, including cycle state information. I'm working on generating a set of these for the 8088. Do …

The 8088 Prefetch Algorithm

Posted on 2023-08-15, 16:01

I'm posting this here as I don't plan to update my blog thread going forward - it's a bit spammy, and after all if you want to follow updates to my blog, an RSS feed is available. But I believe this particular post is of significant interest to mention separately: https://martypc.blogspot.com/2023/ …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-14, 12:56

I've changed a bit of how I handle the BIU state logic. In my previous post, I talked about the BIU "stalling" when the queue is full - I now no longer use this terminology; but the behavior is essentially the same. I now call this the BIU "Idle" state. I'll have a writeup about this soon.

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-11, 11:50

I've just added a neat little feature to UniPCemu's softdebugger: software triggered debugger logging. So software can instruct the debugger to start logging at a specified point in execution and instruct it to stop logging when needed. The basic protocol to set it up is done using a normal …

Re: PCEM Hercules

Posted on 2023-08-07, 17:17

not pcem, but 86box has a 'blend' option enabled by default for hercules, could be something similar going on. I tried it out in prince of persia and with it enabled it almost looks like a 4 color mode. Turning it off gives you 1 bit color like you'd expect.

Calling out Intel documentation on the 8088

Posted on 2023-08-07, 16:59

When you've done enough research on the 8088, some of the things that Intel documentation has to say about it starts to sound a bit... suspect. From the "iAPX 86 88 186 188 User's Manual" section 1-24: If the EU needs access to memory, it may have to wait for up to one clock if the BIU has already …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-07, 14:15

Just implemented an extra timer on the BIU emulation of the 808x: - When T3 is ticked (proceeding onto T4), it will set a flag if the prefetch isn't empty. - When T1 arrives to tick and either said flag is set, or no request is made, an additional check is made before checking the requests from the …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-05, 20:19

I do BIU stalls when - a SUSP microcode operation is issued - the prefetcher attempts a CODE fetch bus cycle when the queue is full Huh? A code fetch bus cycle when the queue is full? Can that even happen? Doesn't the BIU perform a 1-cycle NOP essentially (no bus activity) when the PIQ is full and …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-04, 12:39

I've been thinking... Is there a difference in bus stalls? As in, is a BIU stall and BUS stall the same or are they different in some way internally to the BIU? Edit: As a side note, just implemented DRAM refresh setup for the DMA and PIT (PIT channel 1 and DMA channel 0 only, others unaffected) …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-01, 20:40

What metric cycle count does it expect? I can't find it in previous posts. It's an adjusted delta of PIT ticks. Timer #0 is set at the start and read at the end of the routine. the difference is your 'score'. then an adjustment is made I don't fully understand, but ends up subtracting ~100ish ticks …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-08-01, 20:00

I'd need the raw testcases themselves from 8088 MPH's loader to do that (the part that's being timed for the metric cycle count)? I have cycle traces I can share of the CPU test via MartyPC and reenigne's xtserver, so you don't need to repeat that work, but I'm still in the process of cleaning it …

Re: MartyPC

Posted on 2023-07-31, 20:48

That's not quite what it did, it ticked the device without ticking the CPU. It was pretty specifically built for debugging the end credits of area 5150. It might be back at some point, but my CGA optimizations broke it. Alright, then consider my wrong impression of what it did to be a feature …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-31, 16:20

GloriousCow, I just remember something when reading your article on PC/XT DMA and their T3 behaviour (with it starting DMA at 8088 T3 on an IBM PC, but not XT, due to HLDA behaviour (on T1 in UniPCemu's XT emulation, PC not emulated atm)). No, the difference between PC and XT with DMA is only in …

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