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Reply 100 of 206, by LSS10999

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All the tech docs AMD ever opened up are here. Obviously not as comprehensive as Intel.

It seems with SP5 the LPC bus is totally gone (per SP5's pin map, may also apply to AM5). There's only eSPI.

Reply 101 of 206, by rasteri

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RayeR wrote on 2023-04-06, 13:27:

There's no pin map for AM5 and Pin Description seems to be incomplete, no pin numbers. I don§t understand why AMD turned from open documentation to keep all secret.

In companies like AMD everything is secret by default. There's no real benefit to releasing pinouts, and I bet their legal team can think of 1000 bullshit ways it could bite them on the ass

Reply 102 of 206, by weedeewee

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Is there a list of motherboards on which this ISA adapter has been tested and validated to fully work. It can be added to the first post.

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Reply 103 of 206, by RayeR

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rasteri wrote on 2023-04-06, 16:22:

In companies like AMD everything is secret by default. There's no real benefit to releasing pinouts, and I bet their legal team can think of 1000 bullshit ways it could bite them on the ass

But it was not always for AMD, their older CPUs and chipsets were better/freely documented. Intel seems to me do a constant policy that is more opened except some special documents like BIOS writer's guide and things about trusted/ME/etc...

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Reply 104 of 206, by rasteri

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weedeewee wrote on 2023-04-06, 16:34:

Is there a list of motherboards on which this ISA adapter has been tested and validated to fully work. It can be added to the first post.

so far just GIGABYTE Z77X-D3H, Foxconn H61MXV

Reply 105 of 206, by LSS10999

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rasteri wrote on 2023-04-06, 17:04:
weedeewee wrote on 2023-04-06, 16:34:

Is there a list of motherboards on which this ISA adapter has been tested and validated to fully work. It can be added to the first post.

so far just GIGABYTE Z77X-D3H, Foxconn H61MXV

Hmmm... does the Foxconn one (the one in the OP?) require any modding?

As with most of the boards, modification is needed and the complexity varies among different boards depending how LDRQ# signal is routed.. this needs to be taken into consideration regarding compatibility.

Reply 106 of 206, by ackmangogo

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Got a Asus P8Z77-M board which has tpm header and got coreboot up and running on it, is there a chance working with LPC to ISA bridge?

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Reply 107 of 206, by LSS10999

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ackmangogo wrote on 2023-04-07, 04:38:

Got a Asus P8Z77-M board which has tpm header and got coreboot up and running on it, is there a chance working with LPC to ISA bridge?

If you have the board's boardview, check where your board's LDRQ# signals are. Chances are you may need to manually solder a wire somewhere to access it. If the LDRQ# signal is routed to the TPM header thus directly accessible, then you're lucky -- it can be used without any modification.

Unfortunately boardviews aren't easy to come by. There are some sites hosting them but in most cases they were put behind paywalls of various forms and I'm not sure if they are trustworthy.

Some may be sharing a couple of boardviews through freely accessible means but you are on your own to google for them...

Reply 109 of 206, by LSS10999

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ackmangogo wrote on 2023-04-07, 06:35:

I'm currently using a tool called BoardViewer to look at the files. Don't know if there are any better tools, but this one is simple enough to get started.

I checked your boardview but couldn't find anything explicitly mentioning LDRQ#. Probably undocumented as there are quite a few unnamed nets (Nxxxxxxx).

At least it appears LDRQ# is indeed not routed to the TPM header for your board. You probably have to go through unnamed nets and probably chipset datasheets to determine which one might be LDRQ#.

It seems ASUS boardviews tend to have some undocumented (unnamed) nets. I looked at another ASUS boardview and it was similar -- can't find mentions about LDRQ#, but found a lot of unnamed nets.

ASRock ones are better as their boardviews do mention LDRQ#. I'm currently looking at a board (B450M Pro4-F). In this board's case, the LDRQ# is routed to the SuperIO (NCT6779D) but there are no resistor pads in between... means I'll have to actually lift the SuperIO pin in question and carefully solder a jump wire below, which certainly won't be easy.

Reply 110 of 206, by rasteri

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LSS10999 wrote on 2023-04-07, 03:43:

Hmmm... does the Foxconn one (the one in the OP?) require any modding?

Yeah to enable LDRQ on the TPM header you have to put a blob of solder over a zero-ohm link, and lift the LDRQ pin of the Super I/O chip.

Reply 111 of 206, by weedeewee

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LSS10999 wrote on 2023-04-07, 06:53:

I'm currently using a tool called BoardViewer to look at the files. Don't know if there are any better tools, but this one is simple enough to get started.

Paul Daniels's OpenBoardview (free) / FlexBV

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Reply 112 of 206, by digger

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One thing I'm wondering, though: don't ISA sound cards from back in the day expect an Intel 8237 compatible DMA controller, which would require the RAM to be accessed at 5 MHz? How is this accomplished on the LPC bus, without considerable slowdowns on the system? Sorry if this is a completely clueless question.

Reply 113 of 206, by RayeR

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There's still legacy DMA and PIC somewhere inside chipset and you can probaly tune some timing in registers but LPC is not much faster than old ISA, clock is 33MHz but it's serialized...

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Reply 114 of 206, by EduBat

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The Asus P8Z77-M, as the name implies uses the Z77 chipset.
The datasheet for the same shows that LDRQ1# is assigned to pin BA20 and the boardview shows that pin connected to resistor SR83.

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So, this is where the wire would need to be connected.
The BA20 pin can be configured also as a general GPIO but, since you mention that you use coreboot on your board, as we can see in the gpio.c file, the gpio23 is configured as Native, i.e. LDRQ1# which is excellent.

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Reply 115 of 206, by LSS10999

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rasteri wrote on 2023-04-06, 16:22:
RayeR wrote on 2023-04-06, 13:27:

There's no pin map for AM5 and Pin Description seems to be incomplete, no pin numbers. I don§t understand why AMD turned from open documentation to keep all secret.

In companies like AMD everything is secret by default. There's no real benefit to releasing pinouts, and I bet their legal team can think of 1000 bullshit ways it could bite them on the ass

I think AMD is, in some cases, simply not clear about which exact device (CPU/chipset) a given documentation is meant for, especially when it comes to present day hardware, by using only family and model numbers (codenames for chipsets). Additionally, they seem to document certain components only once unless there's a change somewhere, and it up to the audience to look for the exact one that mentioned the component in question.

(PS: According to some old news regarding the AMD 900 family chipset, the SB900 family southbridges were actually SB800 rebranded. If that's true then it explained why there were no databooks at all about SB900, since the old documents for SB800 would still be valid in this case, and there's no need for them to re-publish the same databooks.)

I did manage to find mentions about Ryzen's LPC controller (1022:790e) in some PPRs only after looking at several of them.

This one is for earlier Zen (17h), and this one is for later Zen (19h). They don't appear to differ much... You can find some other PPRs for some different models of those particular families, but they do not appear to contain sections about the FCH.

NOTE: There is a bit referring to LDRQ#1 in the FCH LPC PCI Config register (D14F3x078), but I couldn't find it on the AM4 pin map. Don't know if that other LDRQ# signal really exists...
EDIT: Nope. There's only one LDRQ# signal. The bit in question could be found in the fam19h PPR, but in the fam17h PPR the same bit was written as "reserved".

weedeewee wrote on 2023-04-07, 12:22:

Paul Daniels's OpenBoardview (free) / FlexBV

By the way... OpenBoardView cannot open fz files by default.

You need to look for a so-called decoding key yourself, and put it into the configuration file.

Reply 116 of 206, by rasteri

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I tried to get it working on the latest version of Debian (32bit), but had mixed results. I was able to get the init program ported easily enough, but then isapnptools wouldn't detect anything.

My guess is that since isapnptools hasn't been updated since 2007 it relies on some now-deprecated gcc feature or kernel API but I didn't do any further investigating.

I suppose next thing to try is a much older version of Linux.

I don't have any non-pnp ISA soundcards (although I theoretically could flash my CS4237-based one to disable PnP).

Reply 117 of 206, by LSS10999

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DracoNihil wrote on 2023-03-24, 01:59:
LSS10999 wrote on 2023-03-24, 01:36:

Still, I wonder if it's possible to probe the LPC controller from Linux (though the controller itself is visible in /sys/devices). I've been looking for tools that could hopefully help me look into the controller but they've so far yielded no usable results... guess I still have to access it from DOS.

Somebody would have to write the tool then. I've never messed around much with /sys/ in Linux but some things can be messed with just by echo'ing certain values to things.

A late answer to this. Actually there's a tool in Linux called "setpci" which can be used to do read/write operations to PCI device registers.

With it, I could actually take a look at the register values of the LPC controller. I haven't tried if it's really possible to write values into it (provided the register in question is r/w), however...