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Cyrix MII-433GP Build

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Reply 100 of 107, by feipoa

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From my testing of about 120 socket 7 CPUs, I feel that for non-overclocked CPUs, and non-AMD CPUs, that the Cyrix MII-433PR was not a bad chip; the gaming benchmark results for the Cyrix were similiar to what Intel put out, although certainly not per-clock. The Cyrix MII-433GP would have needed to immerge at about the time the P233 MMX did to have been of a competitive gaming interest at the time. The latest desktop-intended, non-overclocked Intel P55C was a 233 MHz unit. Likewise for Cyrix, it was the MII-433GP.

To put in some numbers.

Cyrix MII-300 MHz (stock clocked)
Quake2, 640x480: 24 fps

Intel P55C-233MMX (stock clocked)
Quake2, 640x480: 22.7 fps

Cyrix MII-333 MHz (over clocked)
Quake2, 640x480: 24.6 fps

Intel P55C-262MMX (over clocked, stable)
Quake2, 640x480: 23.8 fps

Intel P55C-250MMX (over clocked, stable)
Quake2, 640x480: 25.4 fps

Cyrix MII-350 MHz (way over clocked, instable)
Quake2, 640x480: 26.1 fps

Intel P55C-300MMX (way over clocked, instable)
Quake2, 640x480: 27.3 fps

This is looking mainly at FPU performance in Quake 2, whereby the latest Intel P55C and Cyrix MII were fairly equivalent. The ALU of the last Cyrix will be much better than that of the last P55C. Considering the limited information presented herein, I would lean towards the Cyrix MII-300 MHz as being the overall better processor when compared with the Intel P55C-233 MHz.

I think a comparison of the last VIA Nehemiah 1.4 MHz CPU will not come even remotely close benchmark-wise to the last socket 370 CPU from Intel.

Last edited by feipoa on 2012-09-02, 18:17. Edited 2 times in total.

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Reply 101 of 107, by feipoa

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qfadsf asdfasdf
I can't understand why sometimes the 'delete post' icon is available and sometimes it is not. In the case of this message, it is not.

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Reply 102 of 107, by luckybob

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feipoa wrote:

qfadsf asdfasdf
I can't understand why sometimes the 'delete post' icon is available and sometimes it is not. In the case of this message, it is not.

9TVA0.jpg

It is a mistake to think you can solve any major problems just with potatoes.

Reply 103 of 107, by kool kitty89

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In terms of a good compromise for mainstream gaming performance, general desktop/business application performance, and price/availability, the K6 and K6-2 would obviously have made more sense for most people than either the P55C or MII . . . though in the context of the PR400 (or 433, if you could even find one), the P55C would be a used market CPU and K6 either much faster new (and more expensive than Cyrix) or used market as well, so that historical context isn't quite that straightforward.

Anyway, in terms of "gaming" performance in general, Quake and Quake II may be more extreme examples than most since it's very heavily optimized at low-level for the P5 architecture rather than aiming at broader (or older) x86 optimizations or using even less specific (and usually less optimized) compilers. Quake II was one of the last of its kind too in terms of having a software renderer option that heavily optimized at low-level.
While Cyrix optimized software was next to non-existent, it still may have been possible for less optimized games to fare better in the comparison than the likes of Quake.

There's also the issue of software renderers vs acceleration with more variables there too. You've got the possible optimization issues there too (custom renderer, API, etc), and potentially a wider gap in performance than software rendering as FPU performance alone becomes more important than other tasks needed only for software rendering if the GPU isn't the bottleneck. . . OTOH, software renderers using MMX may widen the gap too with the MII's less powerful MMX unit.

In your tests, it looks like the DirectX based MDK fared a bit better on Cyrix chips vs Pentium than Quake, and directX based games/drivers tend to be less heavily (and less specifically) optimized in general, so this may be part of the reason.

I'm not sure how Unreal might compare overall, and I haven't taken any actual framerate test figures yet, but in terms of general play speed "feel" my Asus P5A-B system running a P55C, MII, and K6, all at 2.5x100 seemed to run pretty close to equal both in software and Glide (Voodoo 3 3000 16MB PCI). though 3DMark99 and Final Reality (software and D3D) showed a major lead for the K6 over the MII and P55C over K6. The K6-2 also didn't seem to be very noticeably faster at the same clock/bus speeds, though it technically should be given the 3DNow! support for Unreal, and purely subjective "look and feel" testing is pretty vague, so I'll have to do more definitive tests later on.

Your 686 benchmark compilation isn't primarily a gaming benchmark though, so expanding it to the necessary sampling for a general overview of late 90s games would be way more work than necessary . . . on top of what you're already doing. Though, on that note, I'm still curious about how slightly older games would compare on these CPU families, specifically the last generation of ALU-only 3D games.

Additionally, I should note that my MII-366 2.9V that I managed to get to 3x100 2.9V (apparently stable) seems to be OK with a typical late-gen K6-2/Celeron capacity heatsink/fan, though it does appear quite temperature sensitive. The MII-366 is supposed to be rated for 70oC max, but at 300 MHz it seems to become unstable somewhere around 55oC. (at/below 50o it's been totally stable so far though)
I also decided to chance it and go all the way to 3.5V with the MII, but achieved nothing stable beyond 3x100, with 333 MHz crashing part way through loading windows and 350 MHz not going past the BIOS.
Note: I'm not using a thermal probe, but going by the motherboard's onboard CPU temp sensor.

The P55C at 3.2V doesn't seem to be nearly as sensitive, but my IBM 6x86L-200+ does seem pretty temp sensitive. At similar temps the MII-2.9V-300MHz (around or below 50C), the 6x86L seems stable at 3x66 MHz at 3.3V (need to test more for the actual stability threshold), but 83x2 also requires a moderate voltage boost for stability (3.0V seemed OK) and 2x95 seemed to be the most finicky to get stable in terms of temp/voltage. Even 95 at 1x required voltage boosts and 100 MHz wouldn't even post reliably at any voltage.

Feipoa, you also mentioned trouble getting your K6-2/550 stable or getting 600 MHz stable at all on a K6. If it's anything like my situation with the Cyrix chips, then temperature sensitivity may be a huge factor there rather than just voltage. Given the stories I've seen with K6-2/550 instability at stock settings (or even 2.4V), the 70C max temp rating is possibly a bit generous, and ample cooling may be the limiting factor for that CPU more than voltage. (unless maybe you were willing to go beyond AMD's 2.5V max rating on the chip and into Cyrix -let alone IDT- levels of voltage on a 250 nm part, and even then, with 2.8+ volts, you'd need adequate cooling to deal with the added wattage anyway)
On an MVP3/4 based board, 124x4.5 or (more likely) 112x5, or roughly similar settings on ALI boards, might also be more achievable (and better performing) than 6x100, but overclocking the chipset with >100 MHz FSB speeds would add another variable to the equation.

Reply 104 of 107, by nforce4max

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The reason why they are so temp sensitive is that internally temps are noticeably higher due to the large dies that most M1 and M2 have. They are also power hungry so some boards could be struggling to keep the cpu fed power wise. One might be able to achieve some decent clocks with a thermocouple or dice.

On a far away planet reading your posts in the year 10,191.

Reply 105 of 107, by feipoa

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kool kitty89 wrote:

you also mentioned trouble getting your K6-2/550 stable or getting 600 MHz stable at all on a K6.

K6-2/550 ran fine after upping the voltage 0.1V from the stated 2.3 V on the chip, so 2.4 V at 550 MHz. K6-2+ ran without issue at 600 MHz. K6-3+/400ATZ, and K6-3+/450ACZ ran fine up to 550 MHz. K6 completed tests at least up to 333 MHz; I did not test beyond that for the K6.

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Reply 106 of 107, by kool kitty89

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feipoa wrote:
kool kitty89 wrote:

you also mentioned trouble getting your K6-2/550 stable or getting 600 MHz stable at all on a K6.

K6-2/550 ran fine after upping the voltage 0.1V from the stated 2.3 V on the chip, so 2.4 V at 550 MHz. K6-2+ ran without issue at 600 MHz. K6-3+/400ATZ, and K6-3+/450ACZ ran fine up to 550 MHz. K6 completed tests at least up to 333 MHz; I did not test beyond that for the K6.

On the note of the K6-III+/450, Red Hill mentioned setting those up as 5x112 (560 MHz) at 2.0V as routine with 1MB cache VA503+ systems. (after a BIOS flash)
Those were also the systems they claimed to be the best possible business multitasking platforms available that they tested at the time.
http://www.redhill.net.au/c/c-e.html

Oddly, there's no mention of overclocking with the K6-2+, though I know it fares about as well as the K6-III+ there.

nforce4max wrote:

The reason why they are so temp sensitive is that internally temps are noticeably higher due to the large dies that most M1 and M2 have. They are also power hungry so some boards could be struggling to keep the cpu fed power wise. One might be able to achieve some decent clocks with a thermocouple or dice.

I think it's more about pushing the chip to the edge of its stability limits, as many overclocked CPUs tend to be more temp sensitive than stock speed ones, for similar reasons as voltage sensitivity. (lower temps and higher voltages both increase the operational limits of circuit function)
Pushing the voltage up still higher made the MII a bit more tolerant to higher temps, but I really didn't want to go past 3.0V for any significant lengths of time. (OTOH, even going to 3.5V wouldn't get it to boot windows at 333 MHz)

With a normal late-gen K6-2/Celeron sized cooler and moderate ambient temps (below 80F), the MII-366 2.9V 3x100 hasn't had any problems in my system. I noticed the stability issues either when I was a passive cooler with no case fan, or with ambient temps above 80F . . . or well above in most cases as we have no air conditioning and it got into the high 80s or low 90s at times in the middle of the day. I didn't notice those problems initially as I'd been testing mostly at night with things much cooler.

On the note of the MII being power hungry, this is mainly due to the high stock voltage ratings used, even though these are 250 nm parts . . . and no other x86 CPUs except IDT's were using such high voltages at that point. The MII is also a somewhat larger chip than the K6 or (to lesser extent) K6-2, but it's mostly the higher voltage that makes the difference. Hence why the 6x86MX/MII's power consumption is only slightly higher than the 2.9V K6's at the same clock speed:
http://www.realworldtech.com/cpu-power-requirements/
(and why the 3.2V K6-233 was so much higher than the 233 MHz MII-300)

I mentioned this to feipoa previously in PM, but I was a little dubious that CPUShack's guide was correct in listing such a large chunk of IBM produced M2s as 250 nm parts given nearly all (save mobiles) were 2.9V parts. So I decided to do some lower voltage testing to see if my 366 (which the guide listed as 250 nm "6+" layer) would run at all at typical 250 nm chip voltages.
I got my MII running down to 2.0V at low clock speeds (I'll need to check, but I think 166 or 180 MHz was the stable limit), and it ran fine at the stock 2.5x100 at 2.2V. Needless to say, it ran much cooler than the stock voltages, similar to a K6-2 at the same speeds. Though I'm pretty sure it's stable temperature limit is well below the manufacturer spec 70C when set to 2.2V, but I haven't really pushed it to instability in that set-up yet.

I'm not entirely sure why Cyrix/IBM resorted to using such high voltages on 250 nm parts when Intel and AMD didn't, or for that matter, why AMD was the only one to resort to 3.2/3.3V for 350 nm parts (and 3.5V for IDT). I'd assume it was largely due to the relatively poor clock speed scaling and yields the M2 core ended up providing compared to K6 or P6 (or P5 for that matter). Possibly Cyrix/IBM also aiming at broader motherboard compatibility (where <2.8V wasn't available).

And I can only guess the added hassle of grading/stess-testing K6s at >2.4/2.5V (and larger cooling/power requirements) and their overall adequate low-voltage yields was why AMD didn't follow that . . . or Intel. AMD and Intel were also quickly reaching much higher clock speeds where voltage boosted parts would have pushed power/cooling requirements above the norm and possibly limited market acceptance, and some motherboards simply may not have been able to handle the power necessary for fast-high-voltage parts. (part of the reason the K6-III never went to 500 MHz iirc) Intel also had the issue of external SRAM speeds with the PII/Katmai (and not wanting to push the Celeron's speed ahead of the PII), but I'm not quite sure why AMD didn't at least push higher voltages with early 250 nm K6/K6-2s, since they didn't even resort to 2.4V until the 400.

I also somehow doubt there was something special about IDT or IBM's 250 nm processes that made their parts more voltage tolerant than Intel or AMD's.

Interestingly enough, Cyrix/VIA also pushed 2.2V standard on their 180 nm parts, well above what Intel or AMD was doing with the K7 or PIII/P4. (K6-+ models were closer to that at 2.0V though)

Reply 107 of 107, by rmay635703

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kool kitty89 wrote on 2012-07-12, 21:46:
Interesting notes on Oddly, they also list the 6x86-80 as 210 mm2 (unlike all other .65 micron entries), and list both the .5 a […]
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Interesting notes on
Oddly, they also list the 6x86-80 as 210 mm2 (unlike all other .65 micron entries), and list both the .5 and .35 micron 6x86Ls as 169 mm2, while making no mention of the .44 micron version.
Assuming that all 3 of those die sizes are legitimate Cyrix figures, but are somewhat mis-labeled/mismatched, it might be the case that the .65 models were 394 mm2, .5 was 210 mm2, .44 was 169 mm2, and the .35 micron models were smaller still but aren't accounted for. (perhaps around 100 mm2)
Those values would all fit reasonably well for die shrinks of those sizes, but I find that 394 mm2 figure a bit strange still, especially with the 5x86 as a workable alternative.

You need to be careful using “die sized” with Cyrix chips as they were very early to slice their dies up into many layers

Comparing the area of a 2 layer chip to a 6+ layer chips is fruitless and doesn’t mean much.