Reply 80 of 82, by PC-Engineer
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Your described problems pointing to an issue with L1:WB in combination with DMA access. This was a common problem in 486 platforms with introducing of WB-CPUs. The WB-mode needs a tight management of changed and writen adresses in RAM and caches. A two layer WB-mode (L1+L2 in WB) in combination with a component, which writes into the RAM in parallel to the CPU and the cache line (called DMA) is not easy to manage. The world of 486 were early pioneers ...