I'm surprised it could not be saved as v4.07. Normally there's a few changes that must be hacked out manually to go down versions. I'm not terribly keen on installing out-of-package software revisions, especially when I don't even see a snap app for the later revision.

I think it fortunate hat I did not pay for their 6-layer board at 10x the cost, as it would also have had the layers missing. Anyone who can do 6-layer cheaper than JLCPCB? I will reply to them that the error is on my part and will see if they offer any refund. I will sit on this for a few days to see if anything else comes up.

I tried save as, and a quick google. maybe I am missing something?

sorry about the messed up gerber output man. we learned a few things from the first prototype though so it wasn't a waste. 😀

If you see anything on the latest pcb version lemme know.

80$ order.. yikes... yes, let's all analyze the latest version for a few days, looking for errors. and cross our fingers that it works :p!

btw, I have an idea for an addition. if someone wants to put together a full parts number list I can try to add it under the socket where it will be covered up by socket. help people assemble easier.

JLCPCB wants $117 CAD, which is $86 USD. I looked at a company in Canada, called Bittele, but they want 4x more than JLCPCB. That's for 10 pieces. There's no point in going lower because the cost doesn't adjust.

I tried to upload the *.rar file to Oshpark, but it said something about the file being unsupported. So I extracted the gerber.zip file and uploaded that. Oshpark wants $54 for 3 pieces, but are we left with that beautiful purple as the only colour option? EDIT: Nope, they aren't letting anyone change the colour or set any options.

It is a .zip now.

Well, we are in prototype stage here, so color doesn't matter.

personally, black would be cool!

What do you mean, you think there's going to be another iteration? At these prices, this is the last order I was intending to put in.

Hard to say man. 😀 so many ideas out there, someone may pop up with another. But I’m looking at this one and liking what I am seeing on my end. Like you said, give it a few days. Let the others take a peek.

But when we are all happy and have a good test I’ll upload a release version and call it π.0

Let’s see how the test with everything assembled and turned on goes.

Sphere478 wrote on 2022-11-01, 21:04:

ChrisK wrote on 2022-11-01, 18:25:

feipoa wrote on 2022-11-01, 12:35:

Where do I buy a paint brush can of silkscreen? And how thick does it go on?

That must be done by Jlcpcb of course.
Just add a simple rectangle over all the pins in the silk screen layer in kicad. Jlcpcb will automatically set the through holes free. The vias will be covered.

So silkscreen cut by solder mask DRCs can be ignored? It won’t paint over the pads?

I don't have the project at hand now, but this is how it looks like on one of my pcbs:

It is basically a simple rectangle drawn over most of the pcb on the silk screen layer (pads must have been cut out directly by KiCAD when I look at the gerbers):

But putting silk screen just over the vias at risk should do the job, too 😀

6-layer costs:
what if you split the pcb in let's say a four layer and a two layer part, and lay it on top of the other before soldering?
Not very elegant and not sure if the routing and the vias in the current design will allow such crazy stuff but should be doable as long as the combined height fits the requirements and vias are only connecting the layers in each of the two pcbs and not going from a layer on one pcb to a layer on the other pcb.
Connections between both pcbs only allowed for through holes.

Price-wise that should come cheaper than a 6-layer design.

Just an idea...

Edit: Nice PiCB version number, btw 😉

ChrisK wrote on 2022-11-02, 07:49:

I don't have the project at hand now, but this is how it looks like on one of my pcbs: SilkScreen_pcb.jpg […]
Show full quote

Sphere478 wrote on 2022-11-01, 21:04:

ChrisK wrote on 2022-11-01, 18:25:

That must be done by Jlcpcb of course.
Just add a simple rectangle over all the pins in the silk screen layer in kicad. Jlcpcb will automatically set the through holes free. The vias will be covered.

So silkscreen cut by solder mask DRCs can be ignored? It won’t paint over the pads?

I don't have the project at hand now, but this is how it looks like on one of my pcbs:
SilkScreen_pcb.jpg

It is basically a simple rectangle drawn over most of the pcb on the silk screen layer (pads must have been cut out directly by KiCAD when I look at the gerbers):
SilkScreen_gerber.jpg

But putting silk screen just over the vias at risk should do the job, too 😀

Excellent!

Sphere478 wrote on 2022-11-02, 18:47:

ChrisK wrote on 2022-11-02, 07:49:

I don't have the project at hand now, but this is how it looks like on one of my pcbs: SilkScreen_pcb.jpg […]
Show full quote

Sphere478 wrote on 2022-11-01, 21:04:

So silkscreen cut by solder mask DRCs can be ignored? It won’t paint over the pads?

I don't have the project at hand now, but this is how it looks like on one of my pcbs:
SilkScreen_pcb.jpg

It is basically a simple rectangle drawn over most of the pcb on the silk screen layer (pads must have been cut out directly by KiCAD when I look at the gerbers):
SilkScreen_gerber.jpg

But putting silk screen just over the vias at risk should do the job, too 😀

Excellent!

Thanks :p

Yeah I thought of a bga setup. It’s not worth the trouble. These are just going to be 80$ for 5 and there isn’t much we can do about it I think. I think it turned out very well. It is a very elegant design to a bowl of spaghetti of a problem. Idk if there is a better way that we could have done this… this result exceeds my initial expectations for sure.

I mean, there is ONE way we could improve, wiring might be tidier if we mounted the socket on the back of the motherboard 🤣. :p

Not quite. The cost is $86 USD + shipping for 10 pieces. With 6 layer, there is no price cut to go for 5 pieces.

I think the product came out looking pretty slick, but it is still untested. If anyone else wants to volunteer testing and put in the order, please let me know.

I received final comment from JLCPCB. They didn't say anything about refunding, however they did provide a tip.

They said, "to avoid there is the same issue next time, please kindly ensure the file is correct before submission, or select the "confirm production file "button, then our system will update the production Gerber file for your checking before producing"

The Englishes isn't perfect, but does it sound like checking the option "confirm production file" = "we will generate missing gerber files"? Or does checking the option "confirm production file" just mean that if there are missing gerbers they will halt production before it starts and get back to the customer?

Sphere, to reduce the risk of coming back empty handed, what do you think about creating those PGA-132 rotator boards to tack onto the next order? I'm sure a lot of people would benefit from these.

Make a thread for it the rotator boards.

I thought I said to check confirm file on the last order? Didn’t you?

Yeah, check that box. It just means they will email you.

Now that we figured out what happened, it makes sense that they may not have caught it. It probably wasn’t totally obvious that there were missing layers on their end.

Just before ordering, we discussed to the contrary of checking 'confirm production file' in hope of improving the probability of getting cheaper boards. See dialogue below. This option is not enabled by default.

feipoa wrote on 2022-10-08, 22:23:

Is the option "Confirm Production file: Yes, No" asking a human at JLCPCB to look at the gerbers for errors, then flag the customer before production? If so, seems like we'd not want to check this.

Sphere478 wrote on 2022-10-08, 23:12:

Yes, you can do that. Go for it :-)

Here's the PGA132 rotator board thread. You don't even need a pinout, just rotate the pins 90, 180, and 270 degrees on 3 different boards. PGA132 rotator boards

Actually I do need a pinout because we need to combine vcc and gnd to make routing easier

I’ll reply in that thread.

Yes you can do that was saying to check it. Sorry communication misunderstanding. I should have clarified.

I could notch upper right for pin 1

Can pull edge back a little on top except where fan memw is

Can round edge corners

Can add pads to bottom of pcb for 5v, gnd, and vcc

Can add part numbers to pcb. (Can someone give full list?)

Of these I gather that you probably like it as is, but part numbers would be good. We can hide them under the socket. So invisible once assembled.

I mentioned earlier that I was having stability issues with my side-by-side interposer in an IBM P70. Vanilla doom ran fine, but basically everything else crashed. I tried fdoom yesterday, which surprisingly froze immediately after startup, not even displaying anything. After some trial and error I landed on a new configuration:

cyrix.exe -f -m- -xA000,64 -cd

Where
-f enables cache
-m- disables caching the first 64k of each Mb
-xA000,64 disables a block of 64k at a specific address. Found this somewhere - without this the cache refuses to work. Seems to have to do something with VGA.
-cd enables clock doubling

With this the cache keeps working (checked it with a doom bench, speed stays same), although it no longer shows in cachecheck. But more important, so far it seems to be completely stable, fdoom starts without a hitch. Will try some more tonight, but wanted to share this to show that the SXL can run stably with our circuit.

Not sure if you were aware I had a write-up on the cyrix.exe settings. Register settings for various CPUs

You generally want to start with disabling caching of the ROM region, 640k - 1024K, so -xA000,128 -xC000,256 which I think is the same as using -r

I would suggest adding several bypass capacitors near the CPU.

elbbar wrote on 2022-11-12, 15:27:

I would suggest adding several bypass capacitors near the CPU.

Must be talking to blavius?

feipoa wrote on 2022-11-12, 12:37:

Not sure if you were aware I had a write-up on the cyrix.exe settings. Register settings for various CPUs

You generally want to start with disabling caching of the ROM region, 640k - 1024K, so -xA000,128 -xC000,256 which I think is the same as using -r

Hey thanks, I didn't yet see that no. I've added the xC000,256. So now I have

cyrix.exe -f -m- -xA000,128 -xC000,256 -cd

Still, not entirely stable unfortunately. While fdoom and vanilla doom now run fine, when I attempt to start C&C I get dos4gw and after a few seconds the harddisk activity stops, the cursurs blinks but the computer does not respond anymore. The stupidest thing is - if after boot I run fdoom first and then start c&c it starts. This works like this every single time I tried it. Not knowing anything about dos4gw, is there any way to figure out what memory chunk I need to exclude to not have this problem?

elbbar wrote on 2022-11-12, 15:27:

I would suggest adding several bypass capacitors near the CPU.

Yeah - this is something that is bugging me. I can never be sure if I'm ironing out some compatibility issue, or if I am dealing with some effect caused by interference. The degree in which the processor works well, and the reproducibility of errors makes me feel this is not very likely the cause though.