I do not know this board but 2nd lvl cache in 486s is always direct mapped.
Maybe there are exceptions but I doubt it... Compaq or Dolch had custom solutions so there could be still some mysteries to be solved.

As a rule of thumb, on a 486, you need 128KB cache for 16MB main in writeback mode(128KB is sufficient for 32MB in write through mode since one tag bit is freed from dirty to adress which yields twice the cachable "size" ).
So, for 8MB main 64KB cache is needed - giving 2^23byte / 2^16byte which yields
2^7byte main / per 2^0 byte cache.
Resulting in a ratio of main : cache of 128:1(256:1 in WriteThrough).

Other vogoners may explan this better and hopefully spot errors.

Agner Fogs https://agner.org/optimize/optimizing_cpp.pdf explains a bit in Chapter 9.1.
This thread may help too https://stackoverflow.com/questions/15937002/ … pped-cache-work

I'm fairly certain my board in question in direct mapped with no funny non-standard stuff happening. And if I read you right, 64K SRAM is best match for a 16MB system.

In writethrough mode - yes.

Forgot to add in my initial post...
Regarding direct mapped cache... this is how I "understood" it.

Your configuration of 64KB 2nd level cache has 4096( 2^16bytes / 2^4 bytes / line) cache lines each 16 bytes - resulting in a [line:byte] adress of [12:4] -> 16 bits.
Add to that the, in writethrough mode, 8 bit that the tag stores you get an [tag:line:byte] -> [8:12:4] adress which is 24bits in size and thus 16MB are addressable in total(from this stems the WriteThrough/WriteBack "formula" for cachable main memory).

The tag's size requirements are another matter and limit how many cache lines can be extended with a tag adress thus limiting your 2nd level cache size.
This results in the tag size requirements for 2nd level cache sizes of
256KB -> 2^18 / 2^4 = 2^14 -> 16KB tag chip
512KB -> 2^19 / 2^4 = 2^15 -> 32KB tag chip
1024KB -> 2^20 / 2^4 = 2^16 -> 64KB tag chip

I decided to revisit this, having just repaired, or, rather, properly reconfigured a board from this family. The above sort of makes sense - but I'm not clear on how the sizes interrelate. Like stated above, it's direct-mapped. And I would assume write-through considering the early era and 386 design cues of this board.

The board can have either 64KB interleaved, 128K non-interleaved, or 256K interleaved L2 cache. Using the following chips.
[qty-8] 8K x 8 = 64KB
[qty-4] 32K x 8 = 128K
[qty-8] 32K x 8 = 256K

The board also has [qty-3] 65536 bit SRAM chips. T55416P-15. Each chip arranged as 16384 words X 4 bits. And these are nested in an area more or less away from the main cache. They are 15ns and seemingly surrounded by a few custom PAL/GAL logic parts in standard DIP sizes. I have no clue how they are wired on the board. I didn't trace anything out.

Can I assume that's TAG RAM? Or maybe it's some weird logic array for the chipset? It's possible to build processors and FPGA-like functionality out of RAM and PALs. So I'm not sure.

Anyhow, the limited charts and documentation talk about selecting 64/128/256 Kb for the L2 cache size. Selectable by jumpers, and interleave controlled by DIP switches. The main L2 array is even highlighted on the diagrams. And everything implies this is user-selectable to 64/128/256 simply by swapping the 8 chips and setting the settings. Nowhere is anything, anything at all, mentioned about TAG RAM or changing the other 3 SRAM chips.

I suppose I should be asking, if that's real TAG RAM, is it sufficient for 256KB? Thoughts and suggestions are the order of the day!

Keatah wrote on 2021-06-19, 23:31:

The board can have either 64KB interleaved, 128K non-interleaved, or 256K interleaved L2 cache. Using the following chips. [qty- […]
Show full quote

The board can have either 64KB interleaved, 128K non-interleaved, or 256K interleaved L2 cache. Using the following chips.
[qty-8] 8K x 8 = 64KB
[qty-4] 32K x 8 = 128K
[qty-8] 32K x 8 = 256K

No surprises here. That's the usual list of configurations possible on early to mid-range 486 boards.

Keatah wrote on 2021-06-19, 23:31:

The board also has [qty-3] 65536 bit SRAM chips. T55416P-15. Each chip arranged as 16384 words X 4 bits. And these are nested in an area more or less away from the main cache. They are 15ns and seemingly surrounded by a few custom PAL/GAL logic parts in standard DIP sizes. I have no clue how they are wired on the board. I didn't trace anything out.

Can I assume that's TAG RAM?

Yes, you can. This is the old tag variant used on many 386 and older 486 mainboards. Two of the three chips are used as 16Kx8 tag ram for up to 256KB of cache. The third chip is used for the dirty indication in write-back mode. Only one of the 4 bits is used. These older chipset need to be able to access the dirty bit with different timing than the tag bits, so it is required to be in a separate chip. This means that (contrary to new boards with a single 16Kx8 or 32Kx8 tag chip), you can have proper write-back cache (with dirty bit support) without losing cachable area. Newer boards repurpose one of the 8 tag bits as dirty bit instead.

Keatah wrote on 2021-06-19, 23:31:

Anyhow, the limited charts and documentation talk about selecting 64/128/256 Kb for the L2 cache size. Selectable by jumpers, and interleave controlled by DIP switches. The main L2 array is even highlighted on the diagrams. And everything implies this is user-selectable to 64/128/256 simply by swapping the 8 chips and setting the settings. Nowhere is anything, anything at all, mentioned about TAG RAM or changing the other 3 SRAM chips.

I suppose I should be asking, if that's real TAG RAM, is it sufficient for 256KB? Thoughts and suggestions are the order of the day!

Yes, exactly. At 256KB cache, you have 16K cache lines, and the three RAM chips are sufficient to manage 16K cache lines. If you have less cache installed, those chips are not used to their full extent. That's what some of the jumpers are for: They choose to what degree these chips are to be used, virtually downgrading them to 8Kx4 in the 128K cache case ans to 4Kx4 in the 64K cache case.

Super! That helps clarify and confirm what I was beginning to think.

So. The third chip in the TAG RAM is for dirty-bits, needed on older chipsets for write-back support for the L2. Alright. Can I assume this MIC 461/462 chipset then supports write-back even though the L1 cache onboard the processor is write-through. If so then I will also assume it's rather sophisticated for its time.

Keatah wrote on 2021-06-21, 07:52:

The third chip in the TAG RAM is for dirty-bits, needed on older chipsets for write-back support for the L2. Alright. Can I assume this MIC 461/462 chipset then supports write-back even though the L1 cache onboard the processor is write-through. If so then I will also assume it's rather sophisticated for its time.

Write-back cache was common on better 386DX cache systems already. As the 386 does not have internal cache, it was not called L2 back then. Chipset designers already had experience with WB cache when the 486 processor came around, so WB was already a common feature on early 486 boards. Sometimes, to save cost, the dirty chip was omitted and hardwired to "always dirty". This configuration is slower than write-through in most applications.

Yes, you are right. 486 boards like yours do support L2 in write-back, and L1 in write-through only. The original 486 pinout / specification was unable to support a L1 cache in write-back mode. Cyrix came up with their own extension to the 486 socket (mostly repurpusing unused pins) to support L1WB, as did AMD. They were not compatible with each other. Intel introduced the Pentium Overdrive supporting L1WB later, and added another row of pins to the processor with the cache control signals. Later when Intel produced the enhanced 486DX4 with L1WB support, the extra row of pins was omitted, and a third layout for L1WB was introduced that was compatible with neither the AMD or the Cyrix pinout. Both AMD and Cyrix switched to the Intel pinout at some point. Some of the later Cyrix processors are labelled with "Standard Pinout" to indicate the Intel pinout. That's why there are tons of jumpers on late 486 mainboards.

The MIC461 chipset most likely doesn't support any of the write-back protocols for the L1WB, and the board likely only has one to three jumpers to select 486SX or 486DX pinout.

Ok thanks on the clarification and explanation. It fits with what I observed and what I might expect. Sooner or later I'll have amassed enough information to make the "missing manual".

Most of the DIPs which are documented are for memory setup.. The remaining 8 or 9 switches are marked as "reserved" DO NOT CHANGE, on the settings charts. One of which is conflictingly marked as either "reserved" or "I/O delay".

There's several default factory soldered-in jumpers like so:

3-position, CLK12. With 1 & 2 closed. Likely set for the 8MHz speed judging by the label.
3-position, SX1. With 2 & 3 closed.
2-position, SX2. With 1 & 2 closed.
3-position, SX3. With 2 & 3 closed.
3-position, unlabeled, no stake connector, no Bergman shunt/cap

There are 3 for cache configuration. These are pointed out in the memory config chart. And they're selectable.

There's a 2-position, unlabeled, no stake connector, no Bergman shunt cap, jumper spot near the CMOS area. Might be for shorting and clearing CMOS.

There's some other unpopulated spots what I think are for 0-Ohm resistors. Larger spacing than jumpers, for more convenient PCB trace routing. Likely for yet more options.

I have a 33MHz version of this board laying around. Would be interesting to compare the two.

NB: Not really looking to hack or overclock this board. It performs pretty well for its speed grade and feature-set. If I need speed I'll just use a modern PC.