Understood. Maybe put a link to your website in the signature? Took me way too long to find the link…

Trying to keep an uncluttered and fairly small signature is a challenge 🤣.

Thänk you very much <3

Tiido wrote:

My 386 board is going to benefit from the extra speed once I start playing with speeds higher that 40MHz. it comes down to what sort of timing settings a particular motherboard offers

I've been a bit overwhelmed with all the options in the bios, especially without any manual ^^ but there are a lot of memory settings there.

rmay635703 wrote:

70ns ram is really only good to 16mhz but can under certain circumstances run synchronized up to 25mhz

No and no. You cannot calculate speeds for async RAM the same way you do for sync. Besides I used 70ns FP memory successfully with a Pentium OverDrive MMX running 66MHz system/memory bus using x-3-3-3 read and x-4-4-4 write timings.

those 3-3-3 and 4-4-4 show that it uses 3 or 4 cycles per successive CAS and that's effective 22 and 16.6MHz access. The 60 and 70ns refer to time from RAS going low to when data is first coming out the data buffers but entire access cycle is nearly twice as long, and page mode accesses (CAS to CAS) are some 40ns and longer (effective 25MHz and slower). Modern memories have only improved the CAS to CAS access speed, which is in single digit ns range but RAS period and RAS to CAS time is still as slow (and much slower in things like GDDR) as these old DRAMs.

ph4nt0m wrote:

rmay635703 wrote:

70ns ram is really only good to 16mhz but can under certain circumstances run synchronized up to 25mhz

No and no. You cannot calculate speeds for async RAM the same way you do for sync. Besides I used 70ns FP memory successfully with a Pentium OverDrive MMX running 66MHz system/memory bus using x-3-3-3 read and x-4-4-4 write timings.

What Tildo has graciously explained is that FPM at one point had to run synchronized to the bus with zero wait states, as technology moved faster than the ram a means to disconnect the memory from the bus speed was needed.
The first attempt was just a wait state after that the memory gained much more complex timings for each aspect of memory behavior.

This is why cache became so important in the 3&486 eras and beyond

The cache became important when CPUs started to run internally faster than system bus. Instruction latencies and throughput were also improved.

Sure you can call async DRAM speeds effective, but those bus cycles are just to match and exceed internal latencies. So, if we have a 70ns FP memory with a 3 cycle CAS to CAS read latency at the 66MHz bus speed, it's like a 45ns SDRAM running at 22MHz. Interleaving could hide a lot of read latency for async DRAMs getting up to a 100% improvement on read bandwidth, but most desktop chipsets knew nothing about it.

Great project,
If you reorder some of the PCBs, I would be interested in 20 to 40 PCBs, to move some chips over from spare PS/2 SIMMs.
eisapc

I'm not sure when new PCBs get ordered, these things are going lot slower than I hoped. I don't have anything against selling blank PCBs though, but they'll certainly cost more than one making their own and ordering them themselves.

SDRAM (that includes DDR and all newer things) quantify their analog characteristics to a clock internally to the chip rather than externally as it would be the case with normal DRAMs and associated controller on the host device, so you have specifications for particular clocks and few adjustable parmeters that will always meet the analog requirements of the actual DRAM cells in the chip. it should be noted that many of the key analog characteristics haven't changed much in the last 30 years (RAS precharge and other RAS related things) and caches solely exist because of these ginormous timespans. Only once first access is completed (takes more than 50ns, but depends on particular chip type) you can finally do fast page mode accesses (the only things that have improved in those years), but in that initial wait a modern CPU can execute thousands of instructions and you absoltuely need caches to allow to maintain instruction throughput. It is why caches are big and cache misses have termendous cost in modern software programming. Also mixed reads and writes completey destroy performance aswell, it isn't entirely wrong to call SDRAMs serial access memories, they are only good at linear accesses within a page.
If you added DDR4 or something to a 486 you will still need traditional caches to maintain performance, simply because the initial access is still as slow as back then...

Maybe somewhat random question, but...

30pin SIMMs theoretically support higher amounts than 4MB. Why was 4MB chosen for the size? Are 8+MB modules less supported by motherboards, or the dram chips are not available to use or something else?
IRC, 16MB was the max for 30pin SIMM?

30pin SIMMs come in 4 varieties, 256KB, 1MB, 4MB and 16MB, each adding one address line over previous, quadrupling the space (DRAMs have address sent in two cycles, half on each). 4MB is supported on many 386 and all 486 boards but definitely not on most/all 286 boards. 16MB support is limited to only late boards from what I have seen, and 16MB sticks are pretty uncommon. Bigger sticks were just not available when the boards not supporting them were made so no support was added or maybe it was only chipset limitation, nobody really knows what was going on when a particular board or chipset was made.

I would make some 16MB ones but finding the right DRAMs to use is not very easy/cost effective and 64MB or even 128MB on a 386 isn't really gonna do a whole lot, 16 or 32MB is already quite plenty haha. For 486 that you absolutely want lot of RAM for you get a board with 72pin SIMMs, those are plentiful and cheap in all but the largest sizes.

@Tiido, thanks for explanation!
I would assume, if older machines just show 16MB sticks as 4MB or 1MB size, that would be fine. But if they would not boot, that would be a problem. Hey, maybe you can add jumpers on address lines to each module to make 16MB stick look like 1 or 4 MB one? (Maybe you can already, just in case, make it for your 4MB module's new pcb, whenever you do it... why not even support 256kB size?)

But, if the dram chips themselves are expensive and hard to get, then this is way harder problem to solve and all above may not be reasonable...

NB! Yes, i myself have a 386 with 8x4MB modules and 486 with 72pin ram. I'm just throwing out some ideas... that you probably have already weighed yourself. 😀

If a motherboard leaves the additional address lines an NCs there will be problems. You should modify the motherboard instead, connect all those additional lines to ground or VCC, whichever is more convenient. I actually had to do this on a 286 board I have here, or it wouldn't boot.

1MB sticks are very plentiful, there's not a whole lot of point turning 4MB or larger one into something less.

Tiido wrote:

1MB sticks are very plentiful, there's not a whole lot of point turning 4MB or larger one into something less.

The idea is to have the same stick for all scenarios. 😜
And your's might be one. With jumpers, you could pull down or up address lines on stick locally maybe.

You still need to solder (there will not be actual jumpers, only maybe solder pads) and if you happen to forget to unshort an address line and put that stick into another machine you'll end up with something that is going to damage whatever it was put into. In theory a pulldown resistor can work but I'm not sure what performance implications will be. I don't add anything that can have negative effect on performance. Modifying the motherboard will still be the best idea.

In other news, I have added 3.3V CPU support to my test motherboard and this means 50MHz bus speed tests will be possible ~
It will be interesting to see how well will these sticks function at 50MHz and what settings are necessary to make them stable. Maybe I'll end up with a few top performer sticks 🤣

BTW one czech guy on oldcomp.cz made his own SIMM module too. You could save time to do the same work twice...
http://oldcomp.cz/viewtopic.php?f=57&t=2907&p … lit=simm#p90428

That design has long thin traces and lot of 90 degree corners which will reduce possible performance. I do like to have logos and "my design" in general, even if it is only theoretically better 🤣.

I have yet to do 50MHz tests, the past weeks have been very busy...

Tiido wrote:

That design has long thin traces and lot of 90 degree corners

all the electrons will fall out 😵

also I like your logo 😀

That was a 1st prototype, just a test if it will work. He wrote that if it works he make new better layout and he probably did. I didn't check later as I still have some spare SIMMs so I'm not personally interested. Anyway in this case the traces on such speed are not critical, traces between SIMM slots and chipsets are many times longer...

Awesome Job! I'd love to buy some but the shipping costs would be pretty insane as always. Did you made the PCB's by yourself or you paided someone to make them?

Also if your mobo doesnt have 30 pin sockets making an 30-pin to 72-pin adapter wouldn't be too difficult to make.