Sphere478 wrote on 2023-02-19, 16:45:
The three chip simms use more address lines than the 9 chip simms to do the same thing. It’s weird, but that’s what the person who makes purple ram told me. And I can confirm my experience on my own motherboard matches this. To get to 32mb I had to use 8 x 9 chip simms
That's misleadingly shortening the issue. The number of address lines is the same, no matter whether you have a 3-chip SIMM or 9-chip SIMM. A 64KB SIMM always uses 8 address lines (MA0-MA7), a 256KB SIMM additionally uses MA8, a 1MB SIMM additionally uses MA9, a 4MB SIMM additionally uses MA10, and a 16MB SIMM additionally uses MA11. The address contacts are multiplexed between a "row" address and a "column" address. Traditional 30-pin SIMMs always use as much address lines during the "row" phase as they use for the "column" phase. For example, a 1MB SIMM uses all ten address lines MA0-MA9 during row address phase, and then again during the column address phase, to yield 20 address bits. And 20 bits are just what you need to select one out of 1.048.576 memory cells.
The issue is bit more involved, though. A RAM chip needs that you refresh every row often enough. The important idea at this point is that not necessarily all address bits that are sent during the "row" phase are used to select a "row" that needs to be refreshed. Around the time when 64 kilobit memory chips got common, DRAM manufacturers figured out that x4 chips are the ones that are most easily built. A x4 chip contains of four identical parts that each input or output a data bit, so that the chip can read or write four bits at once. Physically, the control logic is plus-shaped in the horizontal and vertical center of the chip, and each corner contains the matrix for one of the four bits. A 4 megabit chip just contains of 4 bit fields that each have 1024 rows and 1024 columns. To refresh all rows, you need to refresh rows 0 - 1023. Every refresh cycle will refresh a row in all four fields. This is straight-forward if it is a 1M x 4 chip that has 10 address bits. A chip like this is on 3-chip 1MB modules, but let's talk about 4MB modules, because this thread is titled "4MB SIMMs". A 4 megabit chip can also be a 4M x 1 chip. This chip is read or written as if it only has a single field of 2048 rows and 2048 columns (i.e. 11 bits are sent to the chip both during the column and during the row phase), but internally, it still has the same construction as a 1M x 4 chip. This means there are four fields with just 1024 rows. The top address bit (MA10) during the row address phase is used as a field select bit, as is the top address bit (MA10 again) during the column phase. These two field select bits thus choose which of the four fields you want to interact with. The consequence is that as there are still just 1024 rows physically, it is enough to refresh rows 0-1023 to refresh the complete chip, even though the chip accepts column numbers 0-2047. This kind of chip is used on 9-chip 4MB SIMMs. Each of these chips provides a single bit, for 8 data bits and one parity bit. This means: To properly refresh a 9-chip 4MB SIMMs, you need to refresh rows 0-1023. On the other hand, a 3-chip 4MB SIMM uses two 4M x 4 chips for the data bits. This chip is a 16 megabit chip that consists of four fields of 2048 rows and 2048 columns. This chip thus needs row numbers 0 to 2047 to be refreshed to have the complete chip refreshed.
A board that works with 9-chip 4MB SIMMs, but fails to work with 3-chip 4MB SIMMs thus only has a 10-bit refresh counter and continously refreshes rows 0 to 1023 only. This actually is a common issue on old boards. This also means that the board would be able to work with 3-chip 1MB SIMMs, as those SIMMs also require refresh of rows 0-1023. The "9-chip modules only" rule typically only applies to the biggest size of modules supported. There are more modern refresh schemes that do not depend on the board number to indicate which row to refresh, but only when to refresh the next row. The row number is generated from a counter inside the RAM chip that obviously has enough bits to refresh all rows. These schemes are called "hidden refresh" and "CAS-before-RAS refresh" (aka CBR refresh). If a board uses one of these schemes, it will support 3-chip and 9-chip modules of any size, because the number of address bits during refresh doesn't matter any more. These refresh schemes got widespread on 486 chipsets, you won't typically find them on 286 chipset.
