VOGONS


First post, by mpe

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I've been recently dealing with a bulk number of SRAM chips for my 2MB cache socket 4 system project.

In order to streamline the testing I crated a simple device using my Arduino Mega and wrote a program that tests 28 or 30-pin SRAM chips. Basically it writes data to every address of the SRAM chip and reads it back using different read/write cycles as described in the data sheets.

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It worked great and was a great help compared to testing chips in a motherboard which I was doing before.

I was thinking taking this one step further and create a device to measure/test the minimum access time of SRAM chips. The purpose would be:

1. to compare advertised times with those expected and identify remarked fake chips
2. to handpick chips that perform the best for extreme overclocking.

Obviously the problem is that my Arduino Mega is a 16 MHz device so it doesn't have enough timer precision and instruction latency to deal with nanosecond time intervals on digital outputs needed for testing -10 or -15 ns chips at the maximum rate.

So I need to scale my prototype up a bit. Arduino makes a 84 MHz ARM based device. It is 3.3V, but with some effort could be adapted I think.

But before I burn time and money on this I was wondering if anyone has any thoughts whether this is at all feasible. Is the above board enough beefy enough to communicate with chips at 10ns precision? Or do I need something even better?

Last edited by mpe on 2020-04-19, 19:36. Edited 2 times in total.

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Reply 1 of 15, by Tronix

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mpe wrote on 2020-02-11, 14:51:

But before I burn time and money on this I was wondering if anyone has any thoughts whether this is at all feasible. Is the above board enough beefy enough to communicate with chips at 10ns precision? Or do I need something even better?

Hi,
i didn’t deal with this Atmel Cortex-M3 microcontroller, but I know a little about STM32 - so, MCU core running at 72MHz, 84MHz and more MHz, but GPIO not connected directly to the core. GPIO connected to core over internal MCU system bus in case of STM32 named APH or APB and its speed does not reach the full speed of the MCU core. Moreover, there are many more peripherals on this bus and the bus speed is shared between them all. For ex, STM32F103 core running at 72MHz. GPIO interconnected to core over APB2 system bus clocked sysclk/2=36MHz. GPIO toggle speed via HAL library about 2-3MHz max. Hard-coded assembler can give about 10 MHz.

IMHO ARM Cortex series MCU not the best choice for fast driving IO pins at a given high speed. i think small FPGA or large CPLD+8 bit MCU much more suitable for these purposes.

https://github.com/Tronix286/

Reply 2 of 15, by Tiido

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FPGA based memory tester is in my todo list, but that list is fairly big and I lack money for the time being. SRAM and SIMM testing are the primary goals.

T-04YBSC, a new YMF71x based sound card & Official VOGONS thread about it
Newly made 4MB 60ns 30pin SIMMs ~
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Reply 3 of 15, by H3nrik V!

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Maybe get working with user "xsecret" over at cpu-world.com ..

http://www.cpu-world.com/forum/viewtopic.php?t=29971

Please use the "quote" option if asking questions to what I write - it will really up the chances of me noticing 😀

Reply 5 of 15, by mpe

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Thank you for opinions.

I am a bit scared of FPGA at this point. But perhaps it is just my unfamiliarity with the technology. I like being able to use a general purpose high-level programming (with option to hand-optimise where needed) which I can do on MCUs.

I have done some research and it looks like even the Due board wouldn't be enough. On my board the speed of the digital interface switching is roughly 5us. The 84 MHz Due board could improve that about 4 times. Going low level perhaps I can get to hundreds of ns - but that's still not fast enough.

I found this 600 MHz Teensy 4.0 board which is branded as one of the fastest MCU currently available. Still cheap and easy enough to program. In theory and with careful programming this could get me to the precision I need and hammer these SRAM chips with 10ns pulses....

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Reply 6 of 15, by feipoa

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I think xsecret on cpu-world was planning on adding a response time SRAM tester to his UCA CPU tester, but hard to say if/when this will happen. http://www.cpu-world.com/forum/viewtopic.php?t=29971

I've been wanting an SRAM tester to test the response time of SRAM for ages, not just for the Chinese 10 ns SRAM, but also to see how much drift there is in response time as SRAM ages with the decades. Same interest is true for FPM/EDO memory. As of 8 years ago, I know there was one such SRAM tester for sale from a company who made them, but the cost was around $1000. I can dig up the emails if you are interested. He did say it could test 10 ns SRAM. I don't recall what the lower limit was.

If just testing the response time, perhaps a you could get a proof of concept working with a breadboard, function generator, and oscilloscope?

Plan your life wisely, you'll be dead before you know it.

Reply 7 of 15, by mpe

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That FPGA CPU tester looks great! I personally don't collect old DIP CPU's but this is still very interesting. Once he gets to 486 class CPUs I'll definitely want one.

My naïve plan for the simple access time measuring program for SRAMs is basically do this in a loop:

-> set address -> write -> delay -> set another address -> delay -> write -> read and compare -> decrease the delay and repeat

I assume that as I keep shortening the delay on a fast enough test device, at some point the SRAM chip won't be able to handle the second write and read back the byte that's been written. Then the last successful delay is the access time I look for. I could use an oscilloscope to calibrate the delay loop.

Yes. I will have to solve the 5V to 3.3V interfacing problem as well if using a fast device. I think I will get one of these Teensy 4.0 boards + as couple of transceivers to see what it can do.

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Reply 8 of 15, by feipoa

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They are certainly cheap enough at $20 each. I figured 600 MHz would cost more, esp. for the features it boasts.

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Reply 10 of 15, by mpe

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Not sure if there is any best practice. I think once the shortest access time is found I'd at least once write with that latency to every single address of the chip before concluding it is working. That means at least 32786 sequential writes for 32k chips.

Or use some sort of testing patterns similar to what memtest86 is doing (walking ones, random, etc.) and run it for several minutes.

I had to use some more advanced tests for my functional testing. The simplest read/write test I initially used wasn't failing when an address pin on one of my chips was missing. Simply because the address bit was treated as 0 and read/write operation still succeeded.

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Reply 11 of 15, by mpe

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Slow progress on this project. This is the second version of my SRAM tester prototype.

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Dumped Arduino. Moved to Teensy 4.0 MCU @ 600 MHz which is 33ox faster. Hope it has enough power to benchmark test SRAMs.

Unfortunately, the MCU is not 5V tolerant so had to use transceivers to interface 5V SRAMs to the 3.3V MCU which complicates things slightly...

Last edited by mpe on 2020-04-19, 22:53. Edited 1 time in total.

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Reply 12 of 15, by feipoa

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But at least you could get them in shield form. I'm really looking forward to this. I see you've already sourced the questionable SRAMs!!!

Plan your life wisely, you'll be dead before you know it.

Reply 13 of 15, by ph4nt0m

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Nemo1985 wrote on 2020-02-12, 20:00:

It's an interesting project if it's going to allow chinese chip testing, they sell them as 10ns but I doubt they really are...

For a small fee, they can write whatever you want on these chips 😀

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Reply 14 of 15, by regis440

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Could you share your testing program and wiring of initial version. I have early socket5 motherboard which hanging on POST when cache is enabled. I would create adapter/clip to test these chips without deslodering.

Reply 15 of 15, by mkarcher

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mpe wrote on 2020-02-11, 14:51:

Obviously the problem is that my Arduino Mega is a 16 MHz device so it doesn't have enough timer precision and instruction latency to deal with nanosecond time intervals on digital outputs needed for testing -10 or -15 ns chips at the maximum rate.

While you can't do that, the Arduino is good enough to create test patterns (changing addresses to measure address access time, toggling /OE to measure /OE response time), and then you can hook up a 1GSps digital scope to the toggling line (/OE or A0), and a data bit that should toggle in response. Of course, this requires you to have access to an 1GSps scope, though...