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FIC 386SC - upgrades and testing

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First post, by megatron-uk

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I received this board from Ebay today - it's in nice shape, other than being dusty and having a flat Dallas RTC:

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Initial testing shows that it works as expected:

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I intend to remove the DX-33 and the 20ns of 256KB 64KB cache and replace with a DX-40 and/or DLC-40 and a full set of 15ns cache modules for 256KB. Luckily everything is already socketed on this board - the processor, cache and main oscillator.

But, the odd thing is that this board doesn't display any codes on the diagnostic card as it powers on. It just sits there like this:

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Normally I would expect to see the POST codes flash up as the test progresses, but with this there's nothing; not even a blank 0000 code. Fortunately there doesn't appear to be anything wrong with the board, but it would be useful to know why it doesn't appear to generate codes via the usual mechanism.

Last edited by megatron-uk on 2021-05-04, 22:11. Edited 1 time in total.

Reply 1 of 31, by megatron-uk

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Interestingly this board also runs fine with a v1.65 MR BIOS image and detects as a generic Symphony SL82C461 chipset. No difference in POST card behaviour though, which is weird.

Anyway, next job is to figure out the jumper settings for this board, as, alas, TH99 and UH19 both refer to a "revision B" board that uses resistor packs to configure the cache, not the block of half a dozen or so jumpers that mine (a "revision A") has instead.

Reply 2 of 31, by megatron-uk

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Just tested a Tx486DLC-40 in the motherboard, and with the MR BIOS rom loaded it correctly identifies it and exposes a "Enable/Disable 486 processor cache" option, which is nice.

Can't figure out the cache settings though; as supplied, the board had eight 64k x 8 SRAM modules and two 16k x 4 TAG modules. The TAG config is different to the documentation for the rev "B" board, which apparently only uses a single 32k x 8 TAG for all options, up to and including 256KB.

There's an image of a board configured with what looks like 256KB on UH19, but finding the specs of the TAG that is in use (labelled as "Paradigm pdm41298sa20d") is tricky. I *think* it's a 64k x 4 design....

Reply 3 of 31, by Horun

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Did you try the POST card in other slots ? Have a few boards that will not output in the short 8bit ISA slots but will in the 16bit ones (one is picky and output only specific ones of the 16bit iirc ).....

Hate posting a reply and have to edit it because it made no sense 😁 First computer was an IBM 3270 workstation with CGA monitor. 🤣 Second computer a 286 12Mhz with real IDE drive ! After that came 386, 486, Pentium, P.Pro and everything after....

Reply 4 of 31, by majestyk

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Mine is also the "A2" revision.
Here´s my (working) jumpering for 128K. Maybe you can spot a pattern...

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Reply 5 of 31, by evasive

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So, this is not a match for you 2?
http://www.win3x.org/uh19/motherboard/show/2358
(Note, I relabeled the page, it was saying something else and I added the actual chipset info).

Reply 7 of 31, by megatron-uk

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evasive wrote on 2021-04-30, 07:34:

So, this is not a match for you 2?
http://www.win3x.org/uh19/motherboard/show/2358
(Note, I relabeled the page, it was saying something else and I added the actual chipset info).

It is!

That's the exact match. I looked through all the matching 82C460 Haydn boards and couldn't find a match, that explains it. Cache settings and everything I need! It does indeed confirm the need for (2x) 64k x 4 TAG modules in either 128KB or 256KB mode.

For the BIOS, it's identical in terms of checksum and on-screen identification string to the second one on this page: http://www.win3x.org/uh19/motherboard/show/2362

For reference, the MR BIOS V016B401 file ("Symphony Labs 'HAYDN' SL82C46X 386sx/386DX/486/Cx") works perfectly on the board.

Reply 9 of 31, by megatron-uk

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Front/rear board images:

Edit: Actually, urgh, the board software has done some nasty downsampling to them... I'll try shrinking them by hand....

Last edited by megatron-uk on 2021-04-30, 08:00. Edited 1 time in total.

Reply 10 of 31, by megatron-uk

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Reply 12 of 31, by megatron-uk

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Do note that in the above images I have 256KB of cache fitted, but only jumpered for 64KB, with the original (2x) 16K tag chips fitted (I didn't have any other tag modules available to test it). So don't use it as a reference for how to configure a 256KB configuration - instead refer to the jumper settings on your site.

Last edited by megatron-uk on 2021-04-30, 08:04. Edited 1 time in total.

Reply 14 of 31, by megatron-uk

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Replacement TAG SRAM modules arrived today:

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I can confirm that for a Revision A2 board that following configuration is needed:

- Eight modules of 32k by 8bit (256kbit) cache SRAM (e.g. UMC UM61M256K)

- Two modules of 64k by 4bit (256kbit) TAG SRAM (e.g Samsung KM64258BP)

The latter 64k x 4bit modules are a pain to track down - they're really not very common at all.

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In addition, the correct jumper settings, again for an A2 board, are:

JP34: 2-3
JP29: 2-3
JP30: 2-3
JP37: 1-2
JP38: 2-3

Furthermore, although unlabelled and noted as "Factory configured" in the TH99 jumper guide, I strongly believe that JP33 is the cache wait-state configuration, as per the Revision B board. If that is indeed true, then the configuration is as follows:

JP33: 1-2, 0ws
JP33: 2-3, 1ws

My board came with 20ns rated cache and tag modules and JP33 configured as 2-3. All the new parts are 15ns rated and I have jumpered it as 1-2. Hopefully benchmarks will confirm the status of that setting.

Reply 16 of 31, by megatron-uk

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Unfortunately it's just power on tests for the moment. I'm in the middle of fitting the parts into a "new" case and lack a multi-io card at hand to do any tests.

I do get a good feeling about it though...

Reply 17 of 31, by pshipkov

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Sounds good. Looking forward.

5-6 Symphony boards passed through here already. They are fun.
Some are badass. Some are so-so.
Very recently checked two more of them.
Last week posted info in another thread about 386/486 hybrid one and examined over the weekend this late and very rare VLB fossil from Young Micro Systems based on Haydn's last reincarnation.

It will be interesting to see what story your tells.

retro bits and bytes

Reply 18 of 31, by megatron-uk

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pshipkov wrote on 2021-05-10, 04:00:
Sounds good. Looking forward. […]
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Sounds good. Looking forward.

5-6 Symphony boards passed through here already. They are fun.
Some are badass. Some are so-so.
Very recently checked two more of them.
Last week posted info in another thread about 386/486 hybrid one and examined over the weekend this late and very rare VLB fossil from Young Micro Systems based on Haydn's last reincarnation.

It will be interesting to see what story your tells.

Managed to pull enough parts together to run a few tests with the system this evening.

I'm still trying to find the fastest, still-stable configuration, but so far, whilst configured as a 386DX-40 with the Cyrix DLC FPU, these are the best results so far:

Wolf 3D, 31.7fps
F1GP Bench 1, 56% low to 62% high
3DBench 17.2fps
Landmark 69.93MHz CPU, 129.93MHz FPU
Norton SI 43.0 CPU
Comptest RAM throughput 16900KB/sec

This is all at stock 40MHz clocks right now, although with the ISA clock at either 10 or 13MHz (the system seems reasonably stable at 13MHz, but my CL-GD5428 [which tests as faster than the ET4000AX or Trident 9000] isn't particularly happy all the time at that speed, or, more accurately, the CheckIT video test proves unreliable with that card in at 13MHz.

I'm still compiling DLC-40 test results, but they're looking very good; same story at 13MHz with the video card though.