VOGONS


First post, by mkarcher

User metadata
Rank Oldbie
Rank
Oldbie

Some SIMMs I found in my "box of spare parts" look like this:

1MB_front.jpg
Filename
1MB_front.jpg
File size
677.28 KiB
Views
763 views
File license
Public domain
1MB_back.jpg
Filename
1MB_back.jpg
File size
756.68 KiB
Views
763 views
File license
Public domain

The chip type numbers are quite clear: TC514400AJ is a 1M x 4 DRAM chip by Toshiba, and TC511000AJ is a 1M x 1 DRAM chip by Toshiba, so this module obviously is a 1M x 9 SIMM, i.e. a standard 30-pin SIMM with parity an 1MB capacity. But some things look a bit odd. There are solder jumper pads on a SIMM. This shouldn't happen on quality SIMMs, except for the Presence Detect pins on 72-pin SIMMs. This is not a 72-pin SIMM. And, digging a bit further: The TC514400AJ are in the wrong package! The package most 1M x 4 chips have is the same as the TC511000AJ to the right, called 300-mil wide SOJ 20/26, i.e. 20 pins used from 26 available positions, 3 missing pins in the center on each side. "300 mil" means 0.3 inches. The TC514400AJ (which seem to be very early 1M x 4 chips) should be in 350-mil SOJ 20/26, i.e. slightly wider, but the same number of pins. The greater width (350 instead of 300 mil) was chosen, because they couldn't physically fit 4 million bits into the smaller case. On this module the TC514400AJ are in 400-mil SOJ 24/28! This case is also a standardized JEDEC package, but (drumroll!) for 4M x 4 DRAM chips! This package is only used for early 4M x 4 chips, because with smaller processes, they managed to put 4M x 4 (16 Megabit) into 300-mil SOJ 24/26.

So I traced the module a bit further. The module layout mostly is for a 4MB SIMM, not a 1MB SIMM. The zero-ohm link between the two "TC514400AJ" chips choses the level of the A10 pin (the highest address pin of 4MB chips, which is not present on 1MB chips!). In the current position (center) A10 at the chips is permanently grounded, so if the chips are in fact 4M chips, only the first half of the rows will be used, and only the first half of columns within these rows. In the top position, the A10 pin at the chips is permanently connected to +5V, so only another quarter of the 4M chips is addressable. Only in the bottom position, A10 at the chips would be connected to A10 on the SIMM slot. So this allows the manufacturer of the module to install in the jumper in the lowest position, test the whole 4M address space whether the bottom quarter or top quarter is defect free, and move the jumper to the appropriate position. I am very confident the "TC514400AJ" chips are fake, and they are in fact factory rejects of 4Mx4 chips, and the module manufacturer "salvaged" them by using only a quarter of them. I can't be sure about the parity chip, because 1M x 1 and 4M x 1 chips have exactly the same case, the only difference is the pin tha t is A10 on 4M chips is NC (not connected) on 1M chips. The parity chip might be a genuine Toshiba 1Mx1 part.

There is something more wrong with this module, though: There are unused solder link pads next to the parity chip as well. And there is a second footprint for the parity chip that is not used. The second parity footprint is 400-mil SOJ 24/28 again! So the manufacturer could have placed even more (possibly rejected) 4Mx4 chips onto this PCB. The four unused solder link options between the parity chip and the right data chip chose one of the four data bits from a 4Mx4 chip to be connected to the parity pins on the SIMM. This allows the manufacturer to use a 4Mx4 chip where only one of the four fields is working correctly. But wait, there's more. The well-informed reader already wondered how you can use a x4 chip as parity chip and be compliant to the 30-pin SIMM standard. You can't. The manufacturer didn't even try. The 30-pin SIMM slot is designed in a way that the data to write to the parity chip is input on pin 29, and the data that is read from the parity chip is output on pin 26. This allows mainboard designers to connect the 8 data bits to a non-disableble parity generator chip, and wire the output of the parity generator to pin 29. On memory writes, the level at pin 29 is stored in the RAM. On memory reads, pin 29 is ignored, pin 26 receives the stored parity data, and the mainboard can compare pin 26 and pin 29 to detect parity error. Early 286 mainboards used exactly this design. Now, the issue with x4 chips is that they don't have dedicated "data in" and "data out" pins, whereas x1 chips do. The TC511000 has data in on pin 1 and data out on pin 25 (counting the missing pins, too, so the next-to-last pin in SOJ 20/26). You obviously see a thick trace connecting these pins, that also is connected to the left side of all the solder jumpers for parity bit selection. So the module downgrades the dedicated data in / data out pins of the x1 chip to a combined in/out pin, and allows optional connection of one of the four in/out pins of a x4 chip to the same line. This combined in/out pin is then connected to both parity in (29) and parity out (26) of the SIMM contacts (you can see the trace connecting both pins on the back of the PCB). As result, the parity stuff only works well in designs where no dedicated parity in/parity out is required. Most modern chipsets use a single parity in/out pin, so pin 29 and 26 are connected on the mainboard, too. This parity design works perfectly with those chipsets.

Short summary about the possibilities of this PCB:

  • Whatever you do, this PCB always provides combined parity in/out which is noncompliant.
  • You can use two 4Mx4 chips and a 4Mx1 parity chip onto the PCB, and put the A10 jumper into "A10 as is" mode, to build a 4MB SIMM.
  • You can use two working 4Mx4 chips and one 4Mx4 chip where some bits are damaged, put the A10 jumper into "A10 as is" mode, and select a working bit of the broken 4Mx4 chip as parity bit. This also creates a 4MB SIMM.
  • You can use two defective 4Mx4 chips as data chips and a 4Mx1 parity chip and downgrade the module from 4Mx9 to 1Mx9 using the A10 jumper. If the low quarter or the high quarter of all three chips works, this results in a working 1MB SIMM.
  • In the previous variant, instead of using only a quarter of a 4Mx1 parity chip, you could also use a fully-functional 1Mx1 chip. It just ignores the A10 input generated from the jumper.
  • As a final variant, you can equip the PCB with three 4Mx4 chips, use only the low or high quarter of all of them, and furthermore choose a single bit from the chip used as parity chip. Again, this yields a 1MB SIMM.

As the marking of the TC514400 chips is obviously fake, I don't recommend anyone using modules like this if data integrity is important. Having defective 4Mx4 chips labelled as if they were 1Mx4 chips is obviously meant to distract from the fact that this PCB tries to re-qualify broken chips as (reduced-capacity) legitimate chips. I have no idea how thorough the re-qualification of the 4Mx4 chips was performed by the module manufacturer, but I assume they don't use chip manufacturer grade testing.

I also have kind-of similar 4MB SIMMs at a different location that downgrade 4Mx12 into 4Mx9 or 4Mx8 using solder links. I might post about them in a dedicated post shortly.

Reply 1 of 11, by BitWrangler

User metadata
Rank l33t
Rank
l33t

Since things like that had been happening since the 8 bit days http://www.breakintoprogram.co.uk/computers/z … um/hardware/ram you could almost call it "established industry practice"

It's easy to forget in these days of dirt cheap PCBs that PCBs were not a trivial expense then and but for the oldskool prototype techniques may have had long turnaround times for production, so having options on the PCB rather than having a PCB for each option is not all that weird.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 2 of 11, by mkarcher

User metadata
Rank Oldbie
Rank
Oldbie
BitWrangler wrote on 2021-09-05, 18:17:

Since things like that had been happening since the 8 bit days http://www.breakintoprogram.co.uk/computers/z … um/hardware/ram you could almost call it "established industry practice"

I think demoting a damaged chip to a lower specced chip is perfectly acceptable, if you are testing it as rigerously as the lower specced chip is tested at the factory, and you should be up-front on what you did. The spectrum parts were clearly labelled as half-working 64K chips, and as they were sold by the manufacturer and not re-qualified by a third party, I have good faith that the proclaimed working 32K of those chips is actually working perfectly.

Reply 3 of 11, by retardware

User metadata
Rank Oldbie
Rank
Oldbie

@mkarcher:
Very very nice find and analysis of early counterfeit stuff 😀

@BitWrangler:
Yes, this is "established industry practice".
Commodore was one of the major half-good-stuff distributors: http://www.amiga-stuff.com/hardware/8kx1-dram.html
But I believe to have seen seen odd-sized DRAMs even on Big Blue products.

All big manufacturers sold their part-defective memories this way, not only DRAMs.
The 2758 EPROM for example, is a half-defective 2716.

Other examples are disabled cores on multicore CPUS...

This rejects business is still running.
The big rejects recyclers that do their own "re-qualifying" have made some "reputation" cheating the unsuspecting layman buyers.
I won't call names, but I think you all have observed the SSD recalls of some particular "reputed" companies, which like to file bankruptcy when the "re-qualifying" gamble game with rejects goes bad.

(So I only buy memories from manufacturers who do not need to hide the origin of the chips they use.)

Reply 4 of 11, by mkarcher

User metadata
Rank Oldbie
Rank
Oldbie
retardware wrote on 2021-09-05, 19:04:

But I believe to have seen seen odd-sized DRAMs even on Big Blue products.

Indeed. IBM is known for 32K RAMs as well. But in this case, it wasn't half-bad 64K RAMs, but two piggybacked 16K RAMs with /CAS on two different pins. Of course, -0° has a page about the 4132 chips used by IBM.

Reply 5 of 11, by mkarcher

User metadata
Rank Oldbie
Rank
Oldbie

Here are pictures of another kind of SIMM that seems to use factory reject chips:

4MB_front.JPG
Filename
4MB_front.JPG
File size
203.17 KiB
Views
477 views
File license
Public domain
4MB_back.JPG
Filename
4MB_back.JPG
File size
244.59 KiB
Views
477 views
File license
Public domain

In this case, the memory chips are labelled GP4C4M4F2DJ-6. You can't find a datasheet for these chips, but the pinout shows that they are clearly 4M x 4 chips, which is consistent with "4M4" in the chip type number. The strange thing about these modules is that they have a lot of zero-ohm resistors above the memory chips. Furthermore, the module consists of three x4 chips, so the raw storage of this module is x12, not x9 as usual for 30-pin SIMMs. As parity is not stored in a dedicated x1 chips, the issue about the "parity in" and "parity out" being merged also applies for this module. But this module is in even worse violation of the SIMM specification than the previous ones. But let's take a look at the modules step-by-step. The SMD 0-ohm links above the leftmost chip make three connections between 7 pads, leaving one pad unconnected. The layout is:

RAM DQ0<--->SIMM DQ0 RAM DQ1 SIMM DQ1<--->RAM DQ2 SIMM DQ2<--->RAM DQ3

Here <---> indicates a connection made using a 0-ohm resistor. RAM DQ0..DQ3 are the four data bits of the leftmost RAM chip. SIMM DQ0..DQ2 are the three lowest data bit of the 30-pin SIMM connector. In this case, RAM DQ1 is unconnected, and the other three data bits of the RAM chip are connected to the three lowest SIMM slot data bits. By moving the links around, any one other bit could be unconnected instead of RAM DQ1. For example, if the 0-ohm link between SIMM DQ1 and RAM DQ2 would be moved one step to the left, DQ2 would be unused instead of DQ1. So these jumper links are used to demote the 4Mx4 chip into a 4Mx3 chips, where the excluded bit can been chosen arbitrarily.

The second chip is treated the same way. It is connected to SIMM DQ3..DQ5. The first two chip thus only serve 6 bits, instead of the usual 8 bits which are served by the left two chips on standard 3-chip 30-pin simms. This means the parity bit and the last two data bits are served by the third chip. This is only possible by a second gross violation of the 30-pin SIMM standard: The parity bit is supposed to have its dedicated /CAS pin, sometimes called /CASP (CAS for parity). /CAS does not only strobe the column address, but it also is a kind of write mask / output enable signal. If the last two data bits and the parity bit are stored in the same chip, you can't enable data read/write and parity read/write separately. Looking at the SIMM pads, /CASP is unconnected, as is "parity out". This SIMMs relies on the mainboard connecting "parity in" and "parity out". /CAS for the parity bit is taken from /CAS for the data.

The 0-ohm links above the right-most chips are slightly more complicated. The leftmost 7 pads work just like on the other two chips. They map 3 of the four data bits from the RAM chip to three intermediate lines. Lets call these lines I0..I2: In this case, the seven left-most pads look like this:

RAM DQ0<--->I0 RAM DQ1 I1<--->RAM DQ2 I2<--->RAM DQ3

Again, DQ1 is ignored. In contrast to the left and the central RAM chip, the pads do not connect to SIMM data pins directly. This is where the six right-most pads enter the scene. Their layout is:

I0<--->SIMM DQ6 I1<--->SIMM DQ7 I2<--->SIMM ParityIn

The idea of these pads is that if you want to create non-parity SIMMs, you can leave out the link between I2 and SIMM ParityIn. By moving one or both of the other two links one position to the right, any one of the intermediate traces can be ignored, and the other two intermediate lines are connected to DQ6 and DQ7. This effectively creates a any-2-from-4 mapping for the rightmost chip in the non-parity case, or a any-3-from-4-mapping for the rightmost chip in the parity case.

So these PCBs allow to build 4Mx9 30-pin SIMMs out of three 4Mx4 chips which each have one broken field. Similarly, 4Mx8 SIMMs can be built from two chips with one broken field and one chip with two broken fields.

I own a set of four SIMMs of this kind. Interestingly, these SIMMs pass the standard memtest86+ tests without problems, but reproducibly cause NMIs (due to parity errors) while trying to boot linux. My current hypothesis is that these modules suffer on rowhammer-like deficiencies where a seldomly accessed row shows a bit flip if neighbouring rows are repeatedly accessed. As memtest86 accesses all rows in order, you don't have rowhammer victim rows. These issues in real use of the modules show that even if the modules pass some kinds of tests, the chips are not reliable enough to build working memory modules from them - even with one bit masked out.

As bonus, these SIMMs come with warranty labels:

4MB_warrenty_label.jpg
Filename
4MB_warrenty_label.jpg
File size
388.58 KiB
Views
577 views
File license
Public domain

The upper line of text says "SPE 4MB SIMM MODULE" (the missing E is not a type, in German we spell that word without the final E). The bottom line says (coarsely translated) "WARRANTY VOID WITHOUT THIS LABEL". I have no idea which store originally sold these modules, or how I got them, but possibly someone recognizes the kind of warranty label.

Reply 6 of 11, by retardware

User metadata
Rank Oldbie
Rank
Oldbie

This thread made aware that there is a brand well associated with "special modules" of this kind.
Just look at the "Actcts" modules here, most of them are quite "interesting".
As I have some issue with abused Digital Equipment RAM modules, I'll ask the seller for a comment, too.

Reply 7 of 11, by jakethompson1

User metadata
Rank Oldbie
Rank
Oldbie
mkarcher wrote on 2021-09-09, 23:04:

Here are pictures of another kind of SIMM that seems to use factory reject chips:

I saw in this interview with Chuck Peddle (co-designer of 6502) about a later business he operated assembling SIMMs and DIMMs from reject DRAM chips: https://youtu.be/enHF9lMseP8?t=12584
However, it sounds like it was based on something particular to Micron brand reject chips.

Reply 9 of 11, by retardware

User metadata
Rank Oldbie
Rank
Oldbie
jakethompson1 wrote on 2021-10-29, 20:54:

saw in this interview with Chuck Peddle (co-designer of 6502) about a later business he operated assembling SIMMs and DIMMs from reject DRAM chips: https://youtu.be/enHF9lMseP8?t=12584

Maybe Greenpeace should enter this business?

The yield of 100% perfect chips is sometimes as low as 70-80% even at reputed companies like Micron, and there would be enough chips good enough to be used at 50% or even 25% capacity.
The question now is whether there is proactive engineering so that the bad parts of the chips are being electrically disconnected by some means to save energy (fusing? laser cutting?).
But maybe this is already being done?

I mean, apparently the state-of-the-art is now 32Gbit chips, probably not cheaper than the 1969's first RAM chip (16 nibbles for $99.50) or the first 1kx1 DRAM in 1970, which originally also had a very low yield rate.

Possibly there could be made many 8 or 16Gbit chips from the 32Gbit chip rejects?
Or are the 32Gbit chips actually rejects from a still-secret 64Gbit chip production line, with the few good chips being hoarded for later market release?

Reply 10 of 11, by rasz_pl

User metadata
Rank Oldbie
Rank
Oldbie
mkarcher wrote on 2021-09-09, 23:04:

I own a set of four SIMMs of this kind. Interestingly, these SIMMs pass the standard memtest86+ tests without problems, but reproducibly cause NMIs (due to parity errors) while trying to boot linux. My current hypothesis is that these modules suffer on rowhammer-like deficiencies where a seldomly accessed row shows a bit flip if neighbouring rows are repeatedly accessed. As memtest86 accesses all rows in order, you don't have rowhammer victim rows. These issues in real use of the modules show that even if the modules pass some kinds of tests, the chips are not reliable enough to build working memory modules from them - even with one bit masked out.

memtest86 has a dedicated Test 13 [Hammer Test] https://www.memtest86.com/tech_individual-test-descr.html does it pass?
Have you tried disabling/bypassing ECC and checking if Linux crashes? Might be board problem, bad ECC on one of the modules, or bad Linux ECC handling implementation.

jakethompson1 wrote on 2021-10-29, 20:54:

I saw in this interview with Chuck Peddle (co-designer of 6502) about a later business he operated assembling SIMMs and DIMMs from reject DRAM chips: https://youtu.be/enHF9lMseP8?t=12584
However, it sounds like it was based on something particular to Micron brand reject chips.

Chuck was talking about https://www.spectek.com

SpecTek began at Micron in 1988 as a component-recovery group. In the two decades since its inception, the company has grown from an internal group to a manufacturing division

They used to fix easy cases inhouse and also sell leftover parts below their effort threshold.
https://slashdot.org/comments.pl?sid=143059&cid=11987832

Micron started a group over 15 years ago that tests RAM chips at all stages of production that fails testing. […]
Show full quote

Micron started a group over 15 years ago that tests RAM chips at all stages of production that fails testing.

When I worked there it was called the "Partials Division". This group invented the "audio ram" market. They have a wide ranging sorting and grading process. It is called "SpecTek" I believe now. I sometimes see low end memory modules with SpecTek Ram.
12 years ago, I was production technician in a Surface Mount Assembly division that shared a building with Partials. We used to assemble memory modules and even video cards that used "PC grade" chips from the partials group. Everyone said they were good enough, but personally I have always steered clear of them.
The last year I was at Micron, we had a lot of discussions with NEC, Intel and some Russian Fabs to provide the same services to them. We tested a couple million chips from these companies in tests. Never did hear what the end result was.

In that interview Chuck Peddle says:

We also could use partials that nobody else could use. Because people sometimes will take four working
bits and four working bits, and put them together. But my patent said that if you put three and five, it's
mine. Anything that net use a variable number of patches. We call them patches.

The way he describes it sounds like one of those bullshit patents where you claim technicality (odd number of defect!!1) and hope no one tries invalidating.
https://patents.google.com/patent/USRE39016E1/en

Yep 🙁 There are no claims about odd number of defects, no

if you put three and five, it's mine.

Whats more this patent uses famous "x, but on a computer" formula 🙁 https://www.forbes.com/sites/danielfisher/201 … me-court-rules/

wherein at least one computer is used to automate all of the steps

Described method is what Sinclair implemented and shipped 15 years prior, but "on a module". It claims to patent Testing method to later describe it as

accomplished automatically by computer according to programming methods well-known by those skilled in the data processing arts.

None of the claims describe in detail actual method of testing.

The basic process is illustrated in the flow chart for FIG. 3.

Its a Business method patent masquerading as a technical one(doing things everyone knows how to do, but in particular order), also finally officially invalid since Alice.

Both patching and bit-steering may be done by means of solder dot connections or jumper installations on a printed circuit network.

Description fits those Actcts modules perfectly. Chuck Peddle company might of been Celetronix - one of the patents is assigned to them, they were an EMS provider with huge India operation. Manufactured everything and a kitchen sink

set-top satellite decoders, computers, home electronics, networking and server appliances. The company, for instance, does work for direct-to-home (DTH) service provider EchoStar in the US.
AC/DC and DC/DC power supplies and RFID products; PCB and memory module test and assembly; box-build and systems integration; and supply of design, engineering, and other prototyping services

sold in 2006, around the time Chuck mentions Micron closing partials sales.

I always suspected Topless simms to be recycled partials
https://upload.wikimedia.org/wikipedia/common … n_Atari_STE.jpg
Ill remember to grab a bunch and try cracking few open next time Im in the storage.

Reply 11 of 11, by retardware

User metadata
Rank Oldbie
Rank
Oldbie

@rasz_pl, that are very interesting observations!

Regarding the parity error problem, I am not sure whether parity checking was actually active/enabled in all mobos of the 30pin SIMM generation.
Normally bad memory/parity errors should be noticeable by a beep, the screen going black and a message at the top of the screen "Parity error" or the like, as I remember from my experience in the XT/AT/early 386 era.
But on many 486 I wonder whether it is because of shadow RAM that these tend to just crash or sometimes just print weird stuff on the screen before hanging, or parity checking just ignored. Easily observable when setting fast memory timings with slow RAM modules.

I darkly rememberthe name Spectek and it sounded to me like spooktek, avoided them.
Sadly I do not find very old RAM modulesof them in the G**gle image search.
But I understand very well that they are eager not to be associated with their past 😀

rasz_pl wrote on 2021-11-02, 03:00:

I always suspected Topless simms to be recycled partials
https://upload.wikimedia.org/wikipedia/common … n_Atari_STE.jpg
Ill remember to grab a bunch and try cracking few open next time Im in the storage.

What a pity that I sold my ZMD (Zentrum Mikroelektronik Dresden) topless memory modules to a French chip collector...
The ZMD was the company that produced the East Germany's "Megachip" (1Mx1), with a very poor yield (<20%).
There was a lot of corruption going on there back then. In 1989 or early 1990 a friend from the East Berlin University showed me a bunch of these he obtained via "connections". In the ceramic package with gold lid. Looked nice, except for the crude printing...
So I'd be curious what chips might have been in these ZMD topless modules (photos attached) which I found in a disbanded 1994 Vobis 486 computer, and whether these modules employed a parity generator.
But I have no idea how to remove such a black blob to see what is inside...

Regarding modules with parity generator, which in the early-mid 1990s were advertised and sold as RAM modules with "logic parity", these seem often to be recognizable by the parity generator chip labeled with a"GSM logo".
I guess these are very hard to find and sought for by specialized collectors nowadays.

By the way, I had some communication with Mr. Hänel from ram-co, and he supposes that the Actcts memories might be connected with that CTS corporation which most people knew for their CRT monitors. I'll ask him to look out for modules with the GSM logo chip 😀

Attachments

  • DSCN8815.JPG
    Filename
    DSCN8815.JPG
    File size
    1.28 MiB
    Views
    178 views
    File license
    Public domain
  • DSCN8814.JPG
    Filename
    DSCN8814.JPG
    File size
    1.28 MiB
    Views
    178 views
    File license
    Public domain