Interesting, but for all it's architectural advancement, I don't think it's gonna have a lot more processing power than a P200 say if it's running at 50Mhz.

Edit: oh you get SSE3 though, maybe you can get a HD4670 AGP running on your Socket 7 😁

Seems like you can do a lot with a $1000+ FPGA. Not sure what the price of the XC5VLX330 was originally, but on eBay right now it's $1500 and on Digikey it's nearly $17,000, though that's probably just priced that high because they'd have to spin back up a production line.

Error 0x7CF wrote on 2021-12-31, 14:26:

Seems like you can do a lot with a $1000+ FPGA. Not sure what the price of the XC5VLX330 was originally, but on eBay right now it's $1500 and on Digikey it's nearly $17,000, though that's probably just priced that high because they'd have to spin back up a production line.

Whoa yah that's a bit of a showstopper. It would be nice though if it was easy to part out the bus interface code and use a $100 FPGA to buffer a real Atom CPU

I suspect bus translation of an actual Atom would be quite different from how it was done in the paper.

(Page 6, heading 4. EMULATION ON A PC PLATFORM)

In the Atom processor, one of the uncore functions is to bridge between the Atom core and the processor’s pins. Of particular im […]
Show full quote

In the Atom processor, one of the uncore functions is to
bridge between the Atom core and the processor’s pins. Of
particular importance is the uncore’s responsibility to translate memory access requests from the internal format used
by the MEC (i.e. memory execution cluster as described
in Section 2.2) into the bus transaction format used by the
Atom processor FSB and to manage those transactions in
conformance to the FSB protocol.
In order to run the synthesizable Atom core in the Socket7 based FPGA emulation board (as shown in Figure 2 and
discussed in Section 2.4), we develop a veneer uncore interface to translate between the internal memory access request
signals and the bus transaction signals for the Socket-7 FSB.
As shown in Figure 5, the uncore veneer design consists of
two components. The first component, the signal translator,
translates memory access requests between the MEC format
and the Socket-7 bus format. The second component, the
bus manager, actually implements the state machine honoring the Pentium FSB protocol. More detail on these two
components are as follows.

So basically, they entirely replaced the previously existing FSB logic with the Socket 5/7 interface. The original FSB protocol isn't used at all. The Atom core's internal interface, which would normally be translated into the modern Atom FSB protocol, is instead translated into the P5 protocol.

Not that translating the Atom FSB wouldn't be possible, but the paper and its associated FPGA logic wouldn't provide many hints of how to implement Atom FSB -> Sock5/7 FSB conversion. I'm not familiar with how well Atoms would handle their bus being clocked down to Sock5/7 speeds, and I'm not sure whether a $100 FPGA could handle the translation, though I could imagine it maybe being possible.

A 50MHz Atom actually might perform about on-tier with a Pentium 200, the 50MHz FPGA implementation does support HyperThreading which would help it a bit in multicore-capable environments.

Oh right, so about as much use as a German-English dictionary when we need an English-French one.

The Atom paper references a different one where a research team in 2007 put an original Pentium core on an FPGA in a Socket7 system. They had to underclock the board to 25MHz and it seems the CPU ran at 25MHz as well.

https://www.eecg.utoronto.ca/~yiannac/docs/fpga07.pdf