There were indeed some defective chips among the 256K ones. So I replaced the set with 9 chips that are 100% working in 3 other boards. The errors after a cold start ( "Cache Pattern Test Failure") are gone now, but the address line testing error persists.

So I´ll have to dig a little deeper here. First I had a look at the 430FX chipset documentation. There´s a nice diagram for a 256K L2 cache setup with 8 chips 32Kx8 and one 8kx8 Tag chip:

I first measured ALL the traces connecting the northbridge (green), Tag-RAM (violet), the two octal-bus-transceivers (orange) and the 8 SRAM sockets (blue). All connections are 100% o.k. (I/O-lines, address-lines, write enable, output enable, Vss, Vcc). The wiring between the SRAM-sockets where there are parallel lines for all or some chips is o.k. also)
(I still have to check the traces between the SRAM sockets and the 2 Intel 82438FX buffer chips (red) that connect them to the DRAM slots. But I think any problem there would probably not result in address-line errors during cache-checking.)

Since interrupted traces can be safely ruled out, there could be a faulty bus-transceiver or the northbridge itself could be defective. Because it´s the easier job by far, I´m going to replace the two 3-state bus-tranceivers (74F245) first.

Do a diode mode check. Might find a bad pin driver or receiving pin. Red probe on ground and black on each pin in turn. You will get diode voltage drop.

Cheers,

Thanks for this tip!
I just checked all the outputs (B0:B7) of the two transceivers and there´s a diode voltage drop at all pins except for pin 14 of the left chip.

There are also strange results at the input side. I have ordered some 74F245 (SOIC20 package) over the weekend.

Better late than never - I finally finished this project today.
After replacing the second bus transceiver, L2 cache gets detected correctly now, the system boots with cache enabled and L2 cache is working flawlessly.
This saved me from replacing the Northbridge and/ or the two Intel buffer chips.
What a relief!

But the joy didn´t last long when I found out the ISA bus showed flaky behaviour. With ISA slots populated the system wouldn´t run stable. In the end I had to replace the Southbidge.

When desoldering the chips - carefully not under too much heat, no force - I found the pcb-quality, especially the stability of the traces isn´t very convincing. I had two cases of traces getting dissolved. Asus used quite a poor quality here compared to other manufacturers.

Now everything´s perfect (at least I hope...).

Congratulations on the repair! Just out of curiosity, did you use a hot air station for the flat package SB?

Have you considered soldering synchronous (pipeline burst) cache instead? 😀

@flupke11: Thanks!
My usual way to remove/replace QFP chips is to first cut all pins with a Dremel using a small metal circular saw blade. I cut the pins right where they come out of the chip. After lifting the chip out the remaining parts of the pins on the soldering pads can then be removed / desoldered hasslefree (one by one or in groups) without high temperatures and without applying any force.
After some cleaning I solder the new chip the "oldschool way" with a good flux row by row.

@rasz_pl: Yes I did. But I wasn´t able to find any high resolution pictures of the pipeline burst version of the board. It seems to be quite rare. From what I found there seem to be different jumpers and capacitors / resistors populated.
I also could not be sure if the northbridge was defective before finding the underlying cause of the cache-issue. Modding the cache chips first would have complicated the troubleshooting in this case.

Today I equipped this board with 128MB RAM and did some testing. Apparently the 256 KB L2 cache is able to cache 64MB of 128MB RAM.

I also tested with 512KB L2 cache:

As we know Intel´s FX chipset is limited to a maximum cacheable area of 64MB RAM. I wonder why ASUS bothered to provide (and document in the manual) 32-pin SRAM sockets for 512KB L2 cache when the chipset´s maximum cacheable area is already being covered by 256K L2 cache?

Here´s finally a picture of the whole board:

You actually replaced a south bridge? That's hard core.

Does that board come with some vertically attached voltage regulator module? That's pretty ASUS. But it supports the split voltage that way? Didn't think there were FX boards that do.

majestyk wrote on 2022-04-30, 07:49:

As we know Intel´s FX chipset is limited to a maximum cacheable area of 64MB RAM. I wonder why ASUS bothered to provide (and document in the manual) 32-pin SRAM sockets for 512KB L2 cache when the chipset´s maximum cacheable area is already being covered by 256K L2 cache?

So many good reason for that.
"As we know...", well, top nerds with internet access we are, we do know that. CTCM wasn't around in 1995?

Cache was never a very exact science and so many people didn't know jack about it. German OEM Vobis was notorious for selling early 90s PCs without any installed and I have a 486 VLB motherboard that doesn't even have the sockets.
- Possibly Asus used the same layout for HX chipsets?
- Most likely: The sockets were all needed for 256 kB with 32k8 chips. If the retail customer insisted on installing 256 kB additional cache with no benefit, he'd be ASUS' guest. They're not likely to advertise limitation of their merchandise. 😉
- The option for burst SRAM has a limit for 256 kB, so there's that.

For comparison, my FX board, a Soyo 5TC0:

- Silkscreen for DIL SRAMs and COAST socket with 256 kB...
And it notes the 512 kB option in the manual, as well.

majestyk wrote on 2022-04-30, 07:49:

As we know Intel´s FX chipset is limited to a maximum cacheable area of 64MB RAM. I wonder why ASUS bothered to provide (and document in the manual) 32-pin SRAM sockets for 512KB L2 cache when the chipset´s maximum cacheable area is already being covered by 256K L2 cache?

because more cache is still better? The way I think it works is L2 is n-way associative, so the more cache installed the more potential cache slots = less collisions/evictions.

All intel 430xx are 64MB cacheable limit except 430HX with dual tag sram installed can cache up to 512MB.

Cheers,

I added the header for the VRM module myself. You also have to cut some traces and add a jumperblock to enable split voltage operation.
(I also added the beeper, a socket for the Dallas RTC, the PS2 mouse-connector and replaced the 1000µF capacitors.)

All VIA chipsets of that area (Apollo family) supported at least 512MB RAM, up to 2MB L2 cache and a cacheable area of 512MB or even 1024 MB so maybe system integrators / OEMs welcomed some Intel FX based mainbords that could be promoted as "256 - 512 K L2 cache" - no matter if this really had a significant impact on performance.

The SOYO 5TC0 has a more flexible layout providing a CELP slot, supporting 3.3V and 5V (or mixed) SRAM chips with a seperate voltage regulator. And it´s prepared for a split voltage VRM also...

https://dependency-injection.com/intel-430fx- … riton-l2-cache/

FX was when Intel came to the conclusion buttsexing customers by gatekeeping features was a viable market strategy. This move is why we cant have nice things like ECC on the desktop anymore (ryzen might work but unofficial doesnt count).

There´s a nice Dilbert comic about that:

https://dilbert.com/strip/2009-06-29